From patchwork Wed Nov 23 11:12:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5295 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id BFAB823E07 for ; Wed, 23 Nov 2011 11:13:45 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 79E24A1866E for ; Wed, 23 Nov 2011 11:13:45 +0000 (UTC) Received: by ywb5 with SMTP id 5so1668870ywb.11 for ; Wed, 23 Nov 2011 03:13:45 -0800 (PST) Received: by 10.152.144.136 with SMTP id sm8mr14254573lab.33.1322046824623; Wed, 23 Nov 2011 03:13:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs225909lal; Wed, 23 Nov 2011 03:13:44 -0800 (PST) Received: by 10.68.57.33 with SMTP id f1mr7149594pbq.104.1322046822056; Wed, 23 Nov 2011 03:13:42 -0800 (PST) Received: from VA3EHSOBE010.bigfish.com (va3ehsobe010.messaging.microsoft.com. [216.32.180.30]) by mx.google.com with ESMTPS id d4si3073608pbr.125.2011.11.23.03.13.39 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 23 Nov 2011 03:13:42 -0800 (PST) Received-SPF: neutral (google.com: 216.32.180.30 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.180.30; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.30 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail92-va3-R.bigfish.com (10.7.14.237) by VA3EHSOBE010.bigfish.com (10.7.40.12) with Microsoft SMTP Server id 14.1.225.22; Wed, 23 Nov 2011 11:12:58 +0000 Received: from mail92-va3 (localhost [127.0.0.1]) by mail92-va3-R.bigfish.com (Postfix) with ESMTP id 670DD60164; Wed, 23 Nov 2011 11:16:01 +0000 (UTC) X-SpamScore: 10 X-BigFish: VS10(z1039ozc8kzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail92-va3 (localhost.localdomain [127.0.0.1]) by mail92-va3 (MessageSwitch) id 1322046960660404_29807; Wed, 23 Nov 2011 11:16:00 +0000 (UTC) Received: from VA3EHSMHS015.bigfish.com (unknown [10.7.14.239]) by mail92-va3.bigfish.com (Postfix) with ESMTP id 97AAF4C004C; Wed, 23 Nov 2011 11:16:00 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS015.bigfish.com (10.7.99.25) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 23 Nov 2011 11:12:54 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.339.2; Wed, 23 Nov 2011 05:13:32 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pANBDAMl008802; Wed, 23 Nov 2011 05:13:29 -0600 (CST) From: Richard Zhao To: CC: , , , , , , Subject: [RFC V1 6/8] ARM i.MX: clk: add generic support of gate2b Date: Wed, 23 Nov 2011 19:12:33 +0800 Message-ID: <1322046755-13511-7-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> References: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com gate with two control bits is found in imx5/6 CCGR registers. Signed-off-by: Richard Zhao --- arch/arm/plat-mxc/Kconfig | 4 ++ arch/arm/plat-mxc/Makefile | 1 + arch/arm/plat-mxc/clk-gate2b.c | 88 ++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/clock.h | 22 ++++++++ 4 files changed, 115 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-mxc/clk-gate2b.c diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 87af5a1..423b178 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -110,4 +110,8 @@ config IMX_CLK_PLLV2 bool depends on GENERIC_CLK +config IMX_CLK_GATE2B + bool + depends on GENERIC_CLK + endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 96d45dc..0689e78 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -7,6 +7,7 @@ obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o obj-$(CONFIG_ARM_GIC) += gic.o obj-$(CONFIG_IMX_CLK_PLLV2) += clk-pllv2.o +obj-$(CONFIG_IMX_CLK_GATE2B) += clk-gate2b.o obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o diff --git a/arch/arm/plat-mxc/clk-gate2b.c b/arch/arm/plat-mxc/clk-gate2b.c new file mode 100644 index 0000000..f406508 --- /dev/null +++ b/arch/arm/plat-mxc/clk-gate2b.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2011 Richard Zhao, Linaro + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +#define to_clk_gate2b(ck) container_of(ck, struct clk_gate2b, clk) + +static int clk_gate2b_enable(struct clk *clk) +{ + struct clk_gate2b *gate2b = to_clk_gate2b(clk); + unsigned long flags; + u32 reg; + + if (gate2b->lock) + spin_lock_irqsave(gate2b->lock, flags); + + reg = __raw_readl(gate2b->reg); + reg &= ~(0x3 << gate2b->shift); + reg |= gate2b->val_en << gate2b->shift; + __raw_writel(reg, gate2b->reg); + + if (gate2b->lock) + spin_unlock_irqrestore(gate2b->lock, flags); + + return 0; +} + +static void clk_gate2b_disable(struct clk *clk) +{ + struct clk_gate2b *gate2b = to_clk_gate2b(clk); + unsigned long flags; + u32 reg; + + if (gate2b->lock) + spin_lock_irqsave(gate2b->lock, flags); + + reg = __raw_readl(gate2b->reg); + reg &= ~(0x3 << gate2b->shift); + reg |= gate2b->val_dis << gate2b->shift; + __raw_writel(reg, gate2b->reg); + + if (gate2b->lock) + spin_unlock_irqrestore(gate2b->lock, flags); + +} + +struct clk_hw_ops clk_gate2b_ops = { + .enable = clk_gate2b_enable, + .disable = clk_gate2b_disable, +}; +EXPORT_SYMBOL_GPL(clk_gate2b_ops); + +int clk_gate2b_set_val(struct clk *clk, int en, int dis) +{ + struct clk_gate2b *gate2b = to_clk_gate2b(clk); + unsigned long flags; + u32 reg, val; + + en &= 0x3; + dis &= 0x3; + + if (gate2b->lock) + spin_lock_irqsave(gate2b->lock, flags); + + reg = __raw_readl(gate2b->reg); + val = (reg >> gate2b->shift) & 0x3; + reg &= ~(0x3 << gate2b->shift); + if (val == gate2b->val_en && val != en) + reg |= en << gate2b->shift; + else if (val == gate2b->val_dis && val != dis) + reg |= dis << gate2b->shift; + __raw_writel(reg, gate2b->reg); + gate2b->val_en = en; + gate2b->val_dis = dis; + + if (gate2b->lock) + spin_unlock_irqrestore(gate2b->lock, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(clk_gate2b_set_val); diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 2eb11c7..f62256e 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -87,6 +87,28 @@ extern struct clk_hw_ops clk_pllv2_ops; .base = (_base), \ } +/** + * gate with 2 control bits + * + * @parent the parent clk + * @reg the register address + * @shift control bits offset + * @en_val value when clk enabled + * @dis_val value when clk disabled + */ +struct clk_gate2b { + struct clk clk; + void __iomem *reg; + u8 shift; + u8 val_en:2; + u8 val_dis:2; + spinlock_t *lock; +}; + +extern struct clk_hw_ops clk_gate2b_ops; + +int clk_gate2b_set_val(struct clk *clk, int en, int dis); + #endif /* CONFIG_GENERIC_CLK */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MXC_CLOCK_H__ */