From patchwork Wed Nov 23 11:12:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5294 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B701523E07 for ; Wed, 23 Nov 2011 11:13:43 +0000 (UTC) Received: from mail-gx0-f180.google.com (mail-gx0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 86A5EA1866E for ; Wed, 23 Nov 2011 11:13:43 +0000 (UTC) Received: by mail-gx0-f180.google.com with SMTP id v5so1710751ggn.11 for ; Wed, 23 Nov 2011 03:13:43 -0800 (PST) Received: by 10.152.135.225 with SMTP id pv1mr14118562lab.19.1322046822741; Wed, 23 Nov 2011 03:13:42 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs225907lal; Wed, 23 Nov 2011 03:13:42 -0800 (PST) Received: by 10.52.32.163 with SMTP id k3mr24931415vdi.33.1322046820739; Wed, 23 Nov 2011 03:13:40 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe004.messaging.microsoft.com. [216.32.181.184]) by mx.google.com with ESMTPS id es10si12572459vdb.73.2011.11.23.03.13.40 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 23 Nov 2011 03:13:40 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.181.184; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail176-ch1-R.bigfish.com (10.43.68.250) by CH1EHSOBE008.bigfish.com (10.43.70.58) with Microsoft SMTP Server id 14.1.225.22; Wed, 23 Nov 2011 11:12:59 +0000 Received: from mail176-ch1 (localhost [127.0.0.1]) by mail176-ch1-R.bigfish.com (Postfix) with ESMTP id 639915A04BD; Wed, 23 Nov 2011 11:15:13 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 13, X-FB-DOMAIN-IP-MATCH: fail Received: from mail176-ch1 (localhost.localdomain [127.0.0.1]) by mail176-ch1 (MessageSwitch) id 1322046913216100_7526; Wed, 23 Nov 2011 11:15:13 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.241]) by mail176-ch1.bigfish.com (Postfix) with ESMTP id 2578A2C0042; Wed, 23 Nov 2011 11:15:13 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 23 Nov 2011 11:12:58 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Wed, 23 Nov 2011 05:13:36 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pANBDAMm008802; Wed, 23 Nov 2011 05:13:33 -0600 (CST) From: Richard Zhao To: CC: , , , , , , , Sascha Hauer Subject: [RFC V1 7/8] ARM i.MX: prepare common clk support Date: Wed, 23 Nov 2011 19:12:34 +0800 Message-ID: <1322046755-13511-8-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> References: <1322046755-13511-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com From: Sascha Hauer Add static clock help macros, clock register spinlock. Signed-off-by: Sascha Hauer Signed-off-by: Richard Zhao --- arch/arm/plat-mxc/clock.c | 8 ++++ arch/arm/plat-mxc/include/mach/clock.h | 63 ++++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 2ed3ab1..1973b30 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -41,6 +41,8 @@ #include #include +#ifndef CONFIG_GENERIC_CLK + static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); @@ -199,6 +201,7 @@ struct clk *clk_get_parent(struct clk *clk) return clk->parent; } EXPORT_SYMBOL(clk_get_parent); +#endif /* * Get the resulting clock rate from a PLL register value and the input @@ -244,3 +247,8 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) return ll; } + +#ifdef CONFIG_GENERIC_CLK +DEFINE_SPINLOCK(imx_ccm_lock); +EXPORT_SYMBOL_GPL(imx_ccm_lock); +#endif /* CONFIG_USE_COMMON_STRUCT_CLK */ diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index f62256e..b9cfb46 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -81,9 +81,13 @@ struct clk_pllv2 { extern struct clk_hw_ops clk_pllv2_ops; -#define DEFINE_CLK_PLLV2(name, _parent, _base) \ - struct clk_pllv2 name = { \ - .parent = (_parent), \ +#define DEFINE_CLK_PLLV2(_name, _parent, _base) \ + struct clk_pllv2 _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_pllv2_ops, \ + .parent = _parent, \ + }, \ .base = (_base), \ } @@ -109,6 +113,59 @@ extern struct clk_hw_ops clk_gate2b_ops; int clk_gate2b_set_val(struct clk *clk, int en, int dis); +extern spinlock_t imx_ccm_lock; + +#define DEFINE_CLK_GATE2B(_name, _parent, _reg, _shift) \ + struct clk_gate2b _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_gate2b_ops, \ + .parent = _parent, \ + }, \ + .reg = (_reg), \ + .shift = (_shift) * 2, \ + .val_en = 0x3, \ + .val_dis = 0x0, \ + .lock = &imx_ccm_lock, \ + } + +#define DEFINE_CLK_DIVIDER(_name, _parent, _flags, _reg, _shift, _width) \ + struct clk_divider _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_divider_ops, \ + .parent = _parent, \ + .flags = _flags, \ + }, \ + .reg = (_reg), \ + .shift = (_shift), \ + .width = (_width), \ + .lock = &imx_ccm_lock, \ + } + +#define DEFINE_CLK_MUX(_name, _reg, _shift, _width, _clks) \ + struct clk_mux _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_mux_ops, \ + }, \ + .reg = (_reg), \ + .shift = (_shift), \ + .width = (_width), \ + .clks = (_clks), \ + .num_clks = ARRAY_SIZE(_clks), \ + .lock = &imx_ccm_lock, \ + } + +#define DEFINE_CLK_FIXED(_name, _rate) \ + struct clk_hw_fixed _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_hw_fixed_ops, \ + }, \ + .fixed_rate = (_rate), \ + } + #endif /* CONFIG_GENERIC_CLK */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MXC_CLOCK_H__ */