From patchwork Wed Dec 14 01:26:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5644 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8D6D223E01 for ; Wed, 14 Dec 2011 01:27:03 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 84D0AA18395 for ; Wed, 14 Dec 2011 01:27:03 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id 13so412801eaa.11 for ; Tue, 13 Dec 2011 17:27:03 -0800 (PST) Received: by 10.204.152.138 with SMTP id g10mr106359bkw.36.1323826023303; Tue, 13 Dec 2011 17:27:03 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs97699bkc; Tue, 13 Dec 2011 17:27:03 -0800 (PST) Received: by 10.52.94.227 with SMTP id df3mr3068724vdb.51.1323826021381; Tue, 13 Dec 2011 17:27:01 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com. [216.32.181.181]) by mx.google.com with ESMTPS id hy6si427400vdb.16.2011.12.13.17.27.00 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 17:27:01 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.181.181; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail219-ch1-R.bigfish.com (10.43.68.250) by CH1EHSOBE006.bigfish.com (10.43.70.56) with Microsoft SMTP Server id 14.1.225.23; Wed, 14 Dec 2011 01:27:02 +0000 Received: from mail219-ch1 (localhost [127.0.0.1]) by mail219-ch1-R.bigfish.com (Postfix) with ESMTP id 288B62002AF; Wed, 14 Dec 2011 01:27:02 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 13, X-FB-DOMAIN-IP-MATCH: fail Received: from mail219-ch1 (localhost.localdomain [127.0.0.1]) by mail219-ch1 (MessageSwitch) id 1323826021904138_27097; Wed, 14 Dec 2011 01:27:01 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.251]) by mail219-ch1.bigfish.com (Postfix) with ESMTP id D77D26A0100; Wed, 14 Dec 2011 01:27:01 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 14 Dec 2011 01:27:01 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Tue, 13 Dec 2011 19:26:59 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBE1QoVl015617; Tue, 13 Dec 2011 19:26:56 -0600 (CST) From: Richard Zhao To: CC: , , , , , Subject: [PATCH V3 2/4] dts/imx: rename uart labels to consistent with hw spec Date: Wed, 14 Dec 2011 09:26:45 +0800 Message-ID: <1323826007-17937-3-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323826007-17937-1-git-send-email-richard.zhao@linaro.org> References: <1323826007-17937-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com UART1/UART2/... is more readable than UART0/UART1/... . Remove redundant UART comments. Signed-off-by: Richard Zhao --- arch/arm/boot/dts/imx51-babbage.dts | 6 +++--- arch/arm/boot/dts/imx51.dtsi | 12 ++++++------ arch/arm/boot/dts/imx53-ard.dts | 2 +- arch/arm/boot/dts/imx53-evk.dts | 2 +- arch/arm/boot/dts/imx53-qsb.dts | 2 +- arch/arm/boot/dts/imx53-smd.dts | 6 +++--- arch/arm/boot/dts/imx53.dtsi | 18 +++++++++--------- arch/arm/boot/dts/imx6q-sabreauto.dts | 2 +- arch/arm/boot/dts/imx6q.dtsi | 20 ++++++++++---------- 9 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ed09dc1..564cb8c 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -40,7 +40,7 @@ status = "okay"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { fsl,uart-has-rtscts; status = "okay"; }; @@ -90,12 +90,12 @@ reg = <0x73fa8000 0x4000>; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { fsl,uart-has-rtscts; status = "okay"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 57a790d..6663986 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -14,9 +14,9 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; }; tzic: tz-interrupt-controller@e0000000 { @@ -86,7 +86,7 @@ status = "disabled"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; @@ -171,14 +171,14 @@ status = "disabled"; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 78c949e..2dccce4 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -44,7 +44,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 964743e..5bac4aa 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -75,7 +75,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index cc43bde..5c57c86 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -49,7 +49,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 9e51bc3..c7ee86c 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -39,7 +39,7 @@ status = "okay"; }; - uart2: uart@5000c000 { /* UART3 */ + uart3: uart@5000c000 { fsl,uart-has-rtscts; status = "okay"; }; @@ -90,11 +90,11 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3b15cdc..c10dc1f 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; tzic: tz-interrupt-controller@0fffc000 { @@ -173,14 +173,14 @@ status = "disabled"; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; @@ -226,7 +226,7 @@ status = "disabled"; }; - uart3: uart@53ff0000 { /* UART4 */ + uart4: uart@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; @@ -241,7 +241,7 @@ reg = <0x60000000 0x10000000>; ranges; - uart4: uart@63f90000 { /* UART5 */ + uart5: uart@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index cd11ab0..eef6d64 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -44,7 +44,7 @@ status = "okay"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9d0bf4b..263e8f3 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; cpus { @@ -165,7 +165,7 @@ status = "disabled"; }; - uart0: uart@02020000 { /* UART1 */ + uart1: uart@02020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; @@ -543,28 +543,28 @@ interrupts = <0 18 0x04>; }; - uart1: uart@021e8000 { /* UART2 */ + uart2: uart@021e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; status = "disabled"; }; - uart2: uart@021ec000 { /* UART3 */ + uart3: uart@021ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; status = "disabled"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; status = "disabled"; }; - uart4: uart@021f4000 { /* UART5 */ + uart5: uart@021f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>;