From patchwork Thu Dec 15 01:24:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5736 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C656223E04 for ; Thu, 15 Dec 2011 01:25:11 +0000 (UTC) Received: from mail-ee0-f52.google.com (mail-ee0-f52.google.com [74.125.83.52]) by fiordland.canonical.com (Postfix) with ESMTP id BB571A180DD for ; Thu, 15 Dec 2011 01:25:11 +0000 (UTC) Received: by mail-ee0-f52.google.com with SMTP id e52so1692373eek.11 for ; Wed, 14 Dec 2011 17:25:11 -0800 (PST) Received: by 10.204.133.213 with SMTP id g21mr213495bkt.126.1323912311502; Wed, 14 Dec 2011 17:25:11 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs25768bkc; Wed, 14 Dec 2011 17:25:11 -0800 (PST) Received: by 10.224.34.202 with SMTP id m10mr1949469qad.62.1323912309443; Wed, 14 Dec 2011 17:25:09 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe006.messaging.microsoft.com. [216.32.181.186]) by mx.google.com with ESMTPS id ff1si3327619qab.103.2011.12.14.17.25.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Dec 2011 17:25:09 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.186 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) client-ip=216.32.181.186; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.186 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) smtp.mail=B20223@freescale.com Received: from mail7-ch1-R.bigfish.com (10.43.68.242) by CH1EHSOBE017.bigfish.com (10.43.70.67) with Microsoft SMTP Server id 14.1.225.23; Thu, 15 Dec 2011 01:25:10 +0000 Received: from mail7-ch1 (localhost [127.0.0.1]) by mail7-ch1-R.bigfish.com (Postfix) with ESMTP id A83F842056B; Thu, 15 Dec 2011 01:25:12 +0000 (UTC) X-SpamScore: 7 X-BigFish: VS7(z1039ozzz1202hzz8275dhz2dh2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 13, Received: from mail7-ch1 (localhost.localdomain [127.0.0.1]) by mail7-ch1 (MessageSwitch) id 1323912312438978_24451; Thu, 15 Dec 2011 01:25:12 +0000 (UTC) Received: from CH1EHSMHS023.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.243]) by mail7-ch1.bigfish.com (Postfix) with ESMTP id 62535680042; Thu, 15 Dec 2011 01:25:12 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS023.bigfish.com (10.43.70.23) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 15 Dec 2011 01:25:09 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.355.3; Wed, 14 Dec 2011 19:25:06 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBF1OvgJ018541; Wed, 14 Dec 2011 19:25:04 -0600 (CST) From: Richard Zhao To: CC: , Sascha Hauer , Richard Zhao Subject: [RFC V2 4/8] ARM i.MX: Add generic support for pllv2 Date: Thu, 15 Dec 2011 09:24:51 +0800 Message-ID: <1323912295-21144-4-git-send-email-richard.zhao@freescale.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323912295-21144-1-git-send-email-richard.zhao@freescale.com> References: <1323854638-3455-1-git-send-email-richard.zhao@linaro.org> <1323912295-21144-1-git-send-email-richard.zhao@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com From: Sascha Hauer The pllv2 is found on i.MX5 SoCs. Signed-off-by: Sascha Hauer Signed-off-by: Richard Zhao --- arch/arm/plat-mxc/Kconfig | 4 + arch/arm/plat-mxc/Makefile | 1 + arch/arm/plat-mxc/clk-pllv2.c | 221 ++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/clock.h | 26 ++++ 4 files changed, 252 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-mxc/clk-pllv2.c diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index b3a1f2b..903c15e 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -106,4 +106,8 @@ config IRAM_ALLOC bool select GENERIC_ALLOCATOR +config IMX_CLK_PLLV2 + bool + depends on GENERIC_CLK + endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index b9f0f5f..96d45dc 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -6,6 +6,7 @@ obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o obj-$(CONFIG_ARM_GIC) += gic.o +obj-$(CONFIG_IMX_CLK_PLLV2) += clk-pllv2.o obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o diff --git a/arch/arm/plat-mxc/clk-pllv2.c b/arch/arm/plat-mxc/clk-pllv2.c new file mode 100644 index 0000000..ee94c60 --- /dev/null +++ b/arch/arm/plat-mxc/clk-pllv2.c @@ -0,0 +1,221 @@ +#include +#include +#include +#include +#include + +#include + +#include + +#define to_clk_pllv2(ck) (container_of(clk, struct clk_pllv2, clk)) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ + +static unsigned long clk_pllv2_get_rate(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + unsigned long parent_rate; + struct clk_pllv2 *pll = to_clk_pllv2(clk); + + parent_rate = clk->parent->rate; + + pllbase = pll->base; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * parent_rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + void __iomem *pllbase; + struct clk_pllv2 *pll = to_clk_pllv2(clk); + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + unsigned long parent_rate; + + parent_rate = clk->parent->rate; + + pllbase = pll->base; + + quad_parent_rate = 4 * parent_rate; + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -EINVAL; + pdf--; + + temp64 = rate * (pdf+1) - quad_parent_rate * mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + + return 0; +} + +static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + *prate = 0; + return rate; +} + +static int clk_pllv2_enable(struct clk *clk) +{ + struct clk_pllv2 *pll = to_clk_pllv2(clk); + u32 reg; + void __iomem *pllbase; + int i = 0; + + pllbase = pll->base; + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + do { + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_LRF) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: pll locking failed\n"); + return -EINVAL; + } + + return 0; +} + +static void clk_pllv2_disable(struct clk *clk) +{ + struct clk_pllv2 *pll = to_clk_pllv2(clk); + u32 reg; + void __iomem *pllbase; + + pllbase = pll->base; + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +struct clk_hw_ops clk_pllv2_ops = { + .enable = clk_pllv2_enable, + .disable = clk_pllv2_disable, + .recalc_rate = clk_pllv2_get_rate, + .round_rate = clk_pllv2_round_rate, + .set_rate = clk_pllv2_set_rate, +}; + diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 753a598..2eb11c7 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -23,6 +23,7 @@ #ifndef __ASSEMBLY__ #include +#ifndef CONFIG_GENERIC_CLK struct module; struct clk { @@ -62,5 +63,30 @@ void clk_unregister(struct clk *clk); unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); +#else + +/** + * pll v2 + * + * @clk clock source + * @parent the parent clock + * @base base address of pll registers + * + * PLL clock version two, found on i.MX50/51/53 + */ +struct clk_pllv2 { + struct clk clk; + void __iomem *base; +}; + +extern struct clk_hw_ops clk_pllv2_ops; + +#define DEFINE_CLK_PLLV2(name, _parent, _base) \ + struct clk_pllv2 name = { \ + .parent = (_parent), \ + .base = (_base), \ + } + +#endif /* CONFIG_GENERIC_CLK */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MXC_CLOCK_H__ */