From patchwork Thu Dec 15 07:28:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5748 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 21D3923E10 for ; Thu, 15 Dec 2011 07:28:36 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id E9836A18175 for ; Thu, 15 Dec 2011 07:28:35 +0000 (UTC) Received: by eaak10 with SMTP id k10so1764271eaa.11 for ; Wed, 14 Dec 2011 23:28:35 -0800 (PST) Received: by 10.204.133.213 with SMTP id g21mr421850bkt.126.1323934115621; Wed, 14 Dec 2011 23:28:35 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs32683bkc; Wed, 14 Dec 2011 23:28:35 -0800 (PST) Received: by 10.236.83.112 with SMTP id p76mr2512493yhe.118.1323934113054; Wed, 14 Dec 2011 23:28:33 -0800 (PST) Received: from VA3EHSOBE007.bigfish.com (va3ehsobe006.messaging.microsoft.com. [216.32.180.16]) by mx.google.com with ESMTPS id 24si4103103yhs.67.2011.12.14.23.28.32 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Dec 2011 23:28:33 -0800 (PST) Received-SPF: neutral (google.com: 216.32.180.16 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) client-ip=216.32.180.16; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.16 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) smtp.mail=B20223@freescale.com Received: from mail21-va3-R.bigfish.com (10.7.14.250) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.23; Thu, 15 Dec 2011 07:28:33 +0000 Received: from mail21-va3 (localhost [127.0.0.1]) by mail21-va3-R.bigfish.com (Postfix) with ESMTP id 47AF6680133; Thu, 15 Dec 2011 07:28:37 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275dhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail21-va3 (localhost.localdomain [127.0.0.1]) by mail21-va3 (MessageSwitch) id 1323934116941029_21628; Thu, 15 Dec 2011 07:28:36 +0000 (UTC) Received: from VA3EHSMHS010.bigfish.com (unknown [10.7.14.238]) by mail21-va3.bigfish.com (Postfix) with ESMTP id D213134009A; Thu, 15 Dec 2011 07:28:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS010.bigfish.com (10.7.99.20) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 15 Dec 2011 07:28:31 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Thu, 15 Dec 2011 01:28:30 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBF7SRKg023208; Thu, 15 Dec 2011 01:28:27 -0600 (CST) From: Richard Zhao To: CC: , Richard Zhao , Sascha Hauer , Richard Zhao Subject: [RFC V2 2/8] clk: Add support for simple dividers Date: Thu, 15 Dec 2011 15:28:19 +0800 Message-ID: <1323934105-23255-1-git-send-email-richard.zhao@freescale.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323854638-3455-1-git-send-email-richard.zhao@linaro.org> References: <1323854638-3455-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: freescale.com This patch adds support for the most common type of divider, which expects a register, width and shift values to desacribe the location of the divider. The divider can be zero based or one based (div = reg_val + 1 vs. div = reg_val). Signed-off-by: Sascha Hauer Signed-off-by: Richard Zhao --- drivers/clk/Kconfig | 4 + drivers/clk/Makefile | 1 + drivers/clk/clk-divider.c | 134 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk.h | 48 ++++++++++++++++ 4 files changed, 187 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-divider.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09cc198..3bf7a66 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,10 @@ config GENERIC_CLK_BASIC Allow use of basic, single-function clock types. These common definitions can be used across many platforms. +config GENERIC_CLK_DIVIDER + bool + depends on GENERIC_CLK + config GENERIC_CLK_DEBUG bool "Clock tree representation in debugs" depends on GENERIC_CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 68b20a1..fc71576 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_GENERIC_CLK) += clk.o obj-$(CONFIG_GENERIC_CLK_BASIC) += clk-basic.o +obj-$(CONFIG_GENERIC_CLK_DIVIDER) += clk-divider.o diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c new file mode 100644 index 0000000..d319698 --- /dev/null +++ b/drivers/clk/clk-divider.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * Copyright (C) 2011 Richard Zhao, Linaro + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Standard functionality for the common clock API. + */ +#include +#include +#include + +#define to_clk_divider(ck) container_of(ck, struct clk_divider, clk) + +static unsigned long clk_divider_recalc_rate(struct clk *clk) +{ + struct clk_divider *divider = to_clk_divider(clk); + unsigned long rate = clk->parent->rate; + unsigned int div; + + div = readl(divider->reg) >> divider->shift; + div &= (1 << divider->width) - 1; + + if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED)) + div++; + + return rate / div; +} + +static int clk_divider_bestdiv(struct clk *clk, unsigned long rate, + unsigned long *best_parent_rate) +{ + struct clk_divider *divider = to_clk_divider(clk); + int i, bestdiv = 0; + unsigned long parent_rate, best = 0, now, maxdiv; + + maxdiv = (1 << divider->width); + + if (divider->flags & CLK_DIVIDER_FLAG_ONE_BASED) + maxdiv--; + + if (!(clk->flags & CLK_PARENT_SET_RATE)) { + parent_rate = clk->parent->rate; + bestdiv = parent_rate / rate; + bestdiv = bestdiv == 0 ? 1 : bestdiv; + bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; + goto out; + } + + /* + * The maximum divider we can use without overflowing + * unsigned long in rate * i below + */ + maxdiv = min(ULONG_MAX / rate, maxdiv); + + for (i = 1; i <= maxdiv; i++) { + int div; + parent_rate = clk_round_rate(clk->parent, rate * i); + div = parent_rate / rate; + div = div > maxdiv ? maxdiv : div; + div = div < 1 ? 1 : div; + now = parent_rate / div; + + if (now <= rate && now >= best) { + bestdiv = div; + best = now; + *best_parent_rate = parent_rate; + } + } + + if (!bestdiv) { + bestdiv = (1 << divider->width); + parent_rate = clk_round_rate(clk->parent, 1); + } else { + parent_rate = best * bestdiv; + } + +out: + if (best_parent_rate) + *best_parent_rate = parent_rate; + + return bestdiv; +} + +static long clk_divider_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + unsigned long best_parent_rate; + int div = clk_divider_bestdiv(clk, rate, &best_parent_rate); + if (prate) { + if (best_parent_rate == clk->parent->rate) + *prate = 0; + else + *prate = best_parent_rate; + } + + return best_parent_rate / div; +} + +static int clk_divider_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long best_parent_rate; + struct clk_divider *divider = to_clk_divider(clk); + unsigned int div; + unsigned long flags = 0; + u32 val; + + div = clk_divider_bestdiv(clk, rate, &best_parent_rate); + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + + if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED)) + div--; + + val = readl(divider->reg); + val &= ~(((1 << divider->width) - 1) << divider->shift); + val |= div << divider->shift; + writel(val, divider->reg); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +struct clk_hw_ops clk_divider_ops = { + .recalc_rate = clk_divider_recalc_rate, + .round_rate = clk_divider_round_rate, + .set_rate = clk_divider_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_ops); diff --git a/include/linux/clk.h b/include/linux/clk.h index 6cf3e2b..1fa2bca 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -169,6 +169,54 @@ int clk_register_gate(struct device *dev, const char *name, unsigned long flags, #endif +#ifdef CONFIG_GENERIC_CLK_DIVIDER + +#include + +/** + * clock divider + * + * @clk clock source + * @reg register containing the divider + * @shift shift to the divider + * @width width of the divider + * @lock register lock + * + * This clock implements get_rate/set_rate/round_rate. + * + * The divider is calculated as div = reg_val + 1 + * or if CLK_DIVIDER_FLAG_ONE_BASED is set as div = reg_val + * (with reg_val == 0 considered invalid) + */ +struct clk_divider { + struct clk clk; + void __iomem *reg; + unsigned char shift; + unsigned char width; + spinlock_t *lock; +#define CLK_DIVIDER_FLAG_ONE_BASED (1 << 0) + unsigned int flags; + struct clk_hw *parent; +}; + +extern struct clk_hw_ops clk_divider_ops; + +#define DEFINE_CLK_DIVIDER(_name, _parent, _flags, _reg, _shift, _width, _lock) \ + struct clk_divider _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_divider_ops, \ + .parent = _parent, \ + .flags = _flags, \ + }, \ + .reg = (_reg), \ + .shift = (_shift), \ + .width = (_width), \ + .lock = (_lock), \ + } + +#endif /* CONFIG_GENERIC_CLK_DIVIDER */ + /** * clk_init - initialize the data structures in a struct clk * @dev: device initializing this clk, placeholder for now