From patchwork Thu Dec 15 12:50:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 5763 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5F9B523E0E for ; Thu, 15 Dec 2011 12:51:11 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4FF4CA181C1 for ; Thu, 15 Dec 2011 12:51:11 +0000 (UTC) Received: by eaak10 with SMTP id k10so2081677eaa.11 for ; Thu, 15 Dec 2011 04:51:11 -0800 (PST) Received: by 10.204.157.12 with SMTP id z12mr910085bkw.18.1323953471072; Thu, 15 Dec 2011 04:51:11 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs39986bkc; Thu, 15 Dec 2011 04:51:10 -0800 (PST) Received: by 10.213.7.145 with SMTP id d17mr446202ebd.65.1323953469643; Thu, 15 Dec 2011 04:51:09 -0800 (PST) Received: from eu1sys200aog103.obsmtp.com (eu1sys200aog103.obsmtp.com. [207.126.144.115]) by mx.google.com with SMTP id q28si4826251eea.48.2011.12.15.04.51.06 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Dec 2011 04:51:09 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.115 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.115; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.115 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob103.postini.com ([207.126.147.11]) with SMTP ID DSNKTuntOYMJMd+r9/bf8om0LKqpuJQfbMh4@postini.com; Thu, 15 Dec 2011 12:51:09 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D4948AC; Thu, 15 Dec 2011 12:42:36 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 694F81470; Thu, 15 Dec 2011 12:51:02 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 3DF6124C075; Thu, 15 Dec 2011 13:50:55 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 15 Dec 2011 13:51:01 +0100 From: Linus Walleij To: Cc: Linus Walleij , Rabin Vincent Subject: [PATCH 2/5] ux500: update ASIC detection for U5500 Date: Thu, 15 Dec 2011 13:50:59 +0100 Message-ID: <1323953459-27085-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij This adds a few CPU identification functions for the U5500 variants. Contains portions of code written by Rabin Vincent. Cc: Rabin Vincent Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/include/mach/hardware.h | 10 +++++----- arch/arm/mach-ux500/include/mach/id.h | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 470ac52..b6ba26a 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -10,20 +10,21 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H -/* macros to get at IO space when running virtually +/* + * Macros to get at IO space when running virtually * We dont map all the peripherals, let ioremap do * this for us. We map only very basic peripherals here. */ #define U8500_IO_VIRTUAL 0xf0000000 #define U8500_IO_PHYSICAL 0xa0000000 -/* this macro is used in assembly, so no cast */ +/* This macro is used in assembly, so no cast */ #define IO_ADDRESS(x) \ (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) -/* used by some plat-nomadik code */ +/* Used by some plat-nomadik code */ #define io_p2v(n) __io_address(n) #include @@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE; #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) -#endif - +#endif /* __ASSEMBLY__ */ #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h index 02b541a3..833d6a6 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void) } /* + * 5500 revisions + */ + +static inline bool __attribute_const__ cpu_is_u5500v1(void) +{ + return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u5500v2(void) +{ + return (dbx500_id.revision & 0xf0) == 0xB0; +} + +static inline bool __attribute_const__ cpu_is_u5500v20(void) +{ + return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); +} + +static inline bool __attribute_const__ cpu_is_u5500v21(void) +{ + return cpu_is_u5500() && (dbx500_revision() == 0xB1); +} + +/* * 8500 revisions */