From patchwork Wed Jan 11 14:55:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 6154 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id BEB1023E0E for ; Wed, 11 Jan 2012 14:55:48 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id AD96CA18533 for ; Wed, 11 Jan 2012 14:55:48 +0000 (UTC) Received: by mail-bk0-f52.google.com with SMTP id zu5so737213bkb.11 for ; Wed, 11 Jan 2012 06:55:48 -0800 (PST) Received: by 10.204.38.80 with SMTP id a16mr9850791bke.99.1326293748536; Wed, 11 Jan 2012 06:55:48 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs110604bkc; Wed, 11 Jan 2012 06:55:48 -0800 (PST) Received: by 10.180.106.130 with SMTP id gu2mr19962448wib.6.1326293747136; Wed, 11 Jan 2012 06:55:47 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id x67si788229weq.19.2012.01.11.06.55.46 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jan 2012 06:55:47 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) smtp.mail=daniel.lezcano@linaro.org Received: by wgbdr11 with SMTP id dr11so892501wgb.31 for ; Wed, 11 Jan 2012 06:55:46 -0800 (PST) Received: by 10.180.106.130 with SMTP id gu2mr19962325wib.6.1326293746147; Wed, 11 Jan 2012 06:55:46 -0800 (PST) Received: from localhost.localdomain (AToulouse-159-1-69-110.w92-134.abo.wanadoo.fr. [92.134.92.110]) by mx.google.com with ESMTPS id a6sm4608647wiy.6.2012.01.11.06.55.43 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jan 2012 06:55:45 -0800 (PST) From: Daniel Lezcano To: linux@arm.linux.org.uk Cc: robherring2@gmail.com, khilman@ti.com, len.brown@intel.com, linux-pm@vger.kernel.org, magnus.damm@gmail.com, s.hauer@pengutronix.de, nicolas.ferre@atmel.com, nsekhar@ti.com, linux@maxim.org.za, arnd.bergmann@linaro.org, rob.lee@linaro.org, shawn.guo@freescale.com, linux-arm-kernel@lists.infradead.org, amit.kucheria@linaro.org Subject: [PATCH 1/7] at91 : coding style fixes Date: Wed, 11 Jan 2012 15:55:34 +0100 Message-Id: <1326293740-15735-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1326293740-15735-1-git-send-email-daniel.lezcano@linaro.org> References: <1326293740-15735-1-git-send-email-daniel.lezcano@linaro.org> This patch is mindless and does only fix the line length. The purpose is to facilitate the review of the next patches. Signed-off-by: Daniel Lezcano --- arch/arm/mach-at91/pm.h | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index ce9a206..92d2223 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -20,14 +20,16 @@ static inline u32 sdram_selfrefresh_enable(void) return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ - : : "r" (0)) +#define sdram_selfrefresh_disable(saved_lpr) \ + at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) + +#define wait_for_interrupt_enable() \ + asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ + : : "r" (0)) #elif defined(CONFIG_ARCH_AT91CAP9) #include - static inline u32 sdram_selfrefresh_enable(void) { u32 saved_lpr, lpr; @@ -35,12 +37,16 @@ static inline u32 sdram_selfrefresh_enable(void) saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | + AT91_DDRSDRC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) -#define wait_for_interrupt_enable() cpu_do_idle() +#define sdram_selfrefresh_disable(saved_lpr) \ + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) + +#define wait_for_interrupt_enable() \ + cpu_do_idle() #elif defined(CONFIG_ARCH_AT91SAM9G45) #include @@ -77,6 +83,7 @@ static inline u32 sdram_selfrefresh_enable(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ } while (0) + #define wait_for_interrupt_enable() cpu_do_idle() #else @@ -97,11 +104,15 @@ static inline u32 sdram_selfrefresh_enable(void) saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); lpr = saved_lpr & ~AT91_SDRAMC_LPCB; - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | + AT91_SDRAMC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() cpu_do_idle() +#define sdram_selfrefresh_disable(saved_lpr) \ + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) + +#define wait_for_interrupt_enable() \ + cpu_do_idle() #endif