From patchwork Wed Jan 11 14:55:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 6159 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EE8E123E0E for ; Wed, 11 Jan 2012 14:55:59 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id E47EFA18533 for ; Wed, 11 Jan 2012 14:55:59 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id e12so239857eaa.11 for ; Wed, 11 Jan 2012 06:55:59 -0800 (PST) Received: by 10.204.153.27 with SMTP id i27mr10144763bkw.81.1326293759677; Wed, 11 Jan 2012 06:55:59 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs110613bkc; Wed, 11 Jan 2012 06:55:59 -0800 (PST) Received: by 10.180.102.166 with SMTP id fp6mr2459925wib.9.1326293758277; Wed, 11 Jan 2012 06:55:58 -0800 (PST) Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id u47si787647weq.26.2012.01.11.06.55.57 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jan 2012 06:55:58 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) smtp.mail=daniel.lezcano@linaro.org Received: by mail-we0-f178.google.com with SMTP id p12so799825wer.37 for ; Wed, 11 Jan 2012 06:55:57 -0800 (PST) Received: by 10.216.132.19 with SMTP id n19mr2872398wei.31.1326293757317; Wed, 11 Jan 2012 06:55:57 -0800 (PST) Received: from localhost.localdomain (AToulouse-159-1-69-110.w92-134.abo.wanadoo.fr. [92.134.92.110]) by mx.google.com with ESMTPS id a6sm4608647wiy.6.2012.01.11.06.55.55 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jan 2012 06:55:56 -0800 (PST) From: Daniel Lezcano To: linux@arm.linux.org.uk Cc: robherring2@gmail.com, khilman@ti.com, len.brown@intel.com, linux-pm@vger.kernel.org, magnus.damm@gmail.com, s.hauer@pengutronix.de, nicolas.ferre@atmel.com, nsekhar@ti.com, linux@maxim.org.za, arnd.bergmann@linaro.org, rob.lee@linaro.org, shawn.guo@freescale.com, linux-arm-kernel@lists.infradead.org, amit.kucheria@linaro.org Subject: [PATCH 6/7] at91 : group selfrefresh functions Date: Wed, 11 Jan 2012 15:55:39 +0100 Message-Id: <1326293740-15735-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1326293740-15735-1-git-send-email-daniel.lezcano@linaro.org> References: <1326293740-15735-1-git-send-email-daniel.lezcano@linaro.org> Group in a single function the multiple functions declaration. Signed-off-by: Daniel Lezcano --- arch/arm/mach-at91/pm.h | 105 ++++++++++++++++------------------------------ 1 files changed, 37 insertions(+), 68 deletions(-) diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index b9de247..aaa8e14 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -18,7 +18,13 @@ struct ram_saved { u32 lpr1; }; -#ifdef CONFIG_ARCH_AT91RM9200 +#ifdef CONFIG_ARCH_AT91SAM9263 +/* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; + * handle those cases both here and in the Suspend-To-RAM support. + */ +#warning Assuming EB1 SDRAM controller is *NOT* used +#endif /* * The AT91RM9200 goes into self-refresh mode with this command, and will @@ -32,56 +38,32 @@ struct ram_saved { static inline void sdram_selfrefresh_enable(struct ram_saved *rs) { - rs->lpr0 = at91_sys_read(AT91_SDRAMC_LPR); + u32 lpr0; + +#ifdef CONFIG_ARCH_AT91RM9200 + + lpr0 = at91_sys_read(AT91_SDRAMC_LPR); at91_sys_write(AT91_SDRAMC_LPR, 0); at91_sys_write(AT91_SDRAMC_SRR, 1); -} -static inline void sdram_selfrefresh_disable(struct ram_saved *rs) -{ - at91_sys_write(AT91_SDRAMC_LPR, rs->lpr0); -} - -static inline void wait_for_interrupt_enable(void) -{ - asm volatile ("mcr p15, 0, %0, c7, c0, 4" : : "r" (0)); -} + rs->lpr0 = lpr0; #elif defined(CONFIG_ARCH_AT91CAP9) -static inline void sdram_selfrefresh_enable(struct ram_saved *rs) -{ - u32 lpr; - rs->lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); - lpr = rs->lpr0 & ~AT91_DDRSDRC_LPCB; - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | + lpr0 = rs->lpr0 & ~AT91_DDRSDRC_LPCB; + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0 | AT91_DDRSDRC_LPCB_SELF_REFRESH); -} - -static inline void sdram_selfrefresh_disable(struct ram_saved *rs) -{ - at91_ramc_write(0, AT91_DDRSDRC_LPR, rs->lpr0); -} - -static inline void wait_for_interrupt_enable(void) -{ - cpu_do_idle(); -} - #elif defined(CONFIG_ARCH_AT91SAM9G45) -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void sdram_selfrefresh_enable(struct ram_saved *rs) -{ - /* Those tow values allow us to delay self-refresh activation - * to the maximum. */ - u32 lpr0, lpr1; + /* We manage both DDRAM/SDRAM controllers, we need more than one value + * to remember */ + u32 lpr1; + /* Those two values allow us to delay self-refresh activation + * to the maximum. */ rs->lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); lpr1 = rs->lpr1 & ~AT91_DDRSDRC_LPCB; lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; @@ -93,50 +75,37 @@ static inline void sdram_selfrefresh_enable(struct ram_saved *rs) /* self-refresh mode now */ at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); +#else + rs->lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = rs->lpr0 & ~AT91_SDRAMC_LPCB; + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0 | + AT91_SDRAMC_LPCB_SELF_REFRESH); + +#endif } static inline void sdram_selfrefresh_disable(struct ram_saved *rs) { +#ifdef CONFIG_ARCH_AT91RM9200 + at91_sys_write(AT91_SDRAMC_LPR, rs->lpr0); +#elif defined(CONFIG_ARCH_AT91CAP9) + at91_ramc_write(0, AT91_DDRSDRC_LPR, rs->lpr0); +#elif defined(CONFIG_ARCH_AT91SAM9G45) at91_ramc_write(0, AT91_DDRSDRC_LPR, rs->lpr0); at91_ramc_write(1, AT91_DDRSDRC_LPR, rs->lpr1); -} - -static inline void wait_for_interrupt_enable(void) -{ - cpu_do_idle(); -} - #else - -#ifdef CONFIG_ARCH_AT91SAM9263 -/* - * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; - * handle those cases both here and in the Suspend-To-RAM support. - */ -#warning Assuming EB1 SDRAM controller is *NOT* used + at91_ramc_write(0, AT91_SDRAMC_LPR, rs->lpr0); #endif -static inline void sdram_selfrefresh_enable(struct ram_saved *rs) -{ - u32 lpr; - - rs->lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); - - lpr = rs->lpr0 & ~AT91_SDRAMC_LPCB; - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | - AT91_SDRAMC_LPCB_SELF_REFRESH); -} - -static inline void sdram_selfrefresh_disable(struct ram_saved *rs) -{ - at91_ramc_write(0, AT91_SDRAMC_LPR, rs->lpr0); } static inline void wait_for_interrupt_enable(void) { +#ifdef CONFIG_ARCH_AT91RM9200 + asm volatile ("mcr p15, 0, %0, c7, c0, 4" : : "r" (0)); +#else cpu_do_idle(); -} - #endif +} #endif