From patchwork Tue Jan 31 11:09:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 6467 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DAB36249CD for ; Tue, 31 Jan 2012 11:09:50 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id AAA2BA1837F for ; Tue, 31 Jan 2012 11:09:50 +0000 (UTC) Received: by bkar19 with SMTP id r19so5418306bka.11 for ; Tue, 31 Jan 2012 03:09:50 -0800 (PST) Received: by 10.205.130.12 with SMTP id hk12mr10300024bkc.56.1328008190346; Tue, 31 Jan 2012 03:09:50 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.130.220 with SMTP id u28cs177710bks; Tue, 31 Jan 2012 03:09:50 -0800 (PST) Received: by 10.216.136.132 with SMTP id w4mr8435417wei.53.1328008189109; Tue, 31 Jan 2012 03:09:49 -0800 (PST) Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by mx.google.com with ESMTPS id n44si14797194weq.123.2012.01.31.03.09.48 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 31 Jan 2012 03:09:49 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.212.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wibhm14 with SMTP id hm14so5296398wib.37 for ; Tue, 31 Jan 2012 03:09:48 -0800 (PST) Received: by 10.180.86.105 with SMTP id o9mr33812991wiz.4.1328008188847; Tue, 31 Jan 2012 03:09:48 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id di5sm62004043wib.3.2012.01.31.03.09.46 (version=SSLv3 cipher=OTHER); Tue, 31 Jan 2012 03:09:47 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Bi Junxiao , Rabin Vincent , Tixy , Leif Lindholm , Nicolas Pitre Subject: [PATCH v5] ARM: Add generic instruction opcode manipulation helpers Date: Tue, 31 Jan 2012 11:09:40 +0000 Message-Id: <1328008180-28542-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 This patch adds some endianness-agnostic helpers to convert machine instructions between canonical integer form and in-memory representation. A canonical integer form for representing instructions is also formalised here. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre --- Changes since v1: v5: Avoid inclusion of C headers or definition of the __opcode_* macros when opcodes.h is included in assembler files. Since the __opcode_* macros rely on C declarations, they are not directly usable in assembler anyway. v4: Rebase on top of Leif's patch which created ARM: 7206/1: Add generic ARM instruction set condition code checks. No functional changes. v3: Fix some stupid errors: * remove bogus extra (x) in __opcode_to_mem_arm * fix use of nonexistent "thumb_opcode" argument in __opcode_thumb32_{first,second} which causes these macros to be broken. v2: Remove unnecessary typedef for arm_opcode_t. The general "everything is a word" concept works just fine here -- we don't need a typedef, and people will probably not use it anyway. arch/arm/include/asm/opcodes.h | 59 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index c0efdd6..19c48de 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -17,4 +17,63 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #define ARM_OPCODE_CONDTEST_PASS 1 #define ARM_OPCODE_CONDTEST_UNCOND 2 + +/* + * Opcode byteswap helpers + * + * These macros help with converting instructions between a canonical integer + * format and in-memory representation, in an endianness-agnostic manner. + * + * __mem_to_opcode_*() convert from in-memory representation to canonical form. + * __opcode_to_mem_*() convert from canonical form to in-memory representation. + * + * + * Canonical instruction representation: + * + * ARM: 0xKKLLMMNN + * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 + * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 + * + * There is no way to distinguish an ARM instruction in canonical representation + * from a Thumb instruction (just as these cannot be distinguished in memory). + * Where this distinction is important, it needs to be tracked separately. + * + * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not + * represent any valid Thumb-2 instruction. For this range, + * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. + */ + +#ifndef __ASSEMBLY__ + +#include +#include + +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define __opcode_to_mem_arm(x) swab32(x) +#define __opcode_to_mem_thumb16(x) swab16(x) +#define __opcode_to_mem_thumb32(x) swahb32(x) +#else +#define __opcode_to_mem_arm(x) ((u32)(x)) +#define __opcode_to_mem_thumb16(x) ((u16)(x)) +#define __opcode_to_mem_thumb32(x) swahw32(x) +#endif + +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) + +/* Operations specific to Thumb opcodes */ + +/* Instruction size checks: */ +#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL) +#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL) + +/* Operations to construct or split 32-bit Thumb instructions: */ +#define __opcode_thumb32_first(x) ((u16)((x) >> 16)) +#define __opcode_thumb32_second(x) ((u16)(x)) +#define __opcode_thumb32_compose(first, second) \ + (((u32)(u16)(first) << 16) | (u32)(u16)(second)) + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ARM_OPCODES_H */