From patchwork Wed Apr 18 15:30:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 7936 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D2CA923E49 for ; Wed, 18 Apr 2012 15:31:28 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 7B6D7A1820D for ; Wed, 18 Apr 2012 15:31:28 +0000 (UTC) Received: by yhpp61 with SMTP id p61so4637290yhp.11 for ; Wed, 18 Apr 2012 08:31:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=vtGB1utu/KCorN09lXtt8Fs7PA+xiuZt3dsjtP5RW00=; b=pQ/yCKjtcfw6clrfeQ5LiUiUsjmIdrSeAdhNhGUZvufYrdElUBK/pj+IgsgUKUiIkA D4Pp9Z+Qi9lDyOI/V960O/qD625+rOZPEHZGdPasYCMhkKgOhnioIq333NCQX2DV0yZP +xgOtqFJw14z0RKekT4VX196m6q5g8/W8lkuLX+4jXTW3nXemB3zKo4yfpXU1z36EQ8o 6rw+hjoT7LQIuDwzPz/+gzEasOafNbXOomt9hlrMbmLUAAhIpggdUe0XKb+6kBpYNmwK BmfduQOtp5m2zPoNspCqSogSahJyBEbiGD47VtECT7A4OwY4iLnnaAy7XcsJ1poe3LZW wiKQ== Received: by 10.50.196.230 with SMTP id ip6mr2424870igc.49.1334763087585; Wed, 18 Apr 2012 08:31:27 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp225277ibt; Wed, 18 Apr 2012 08:31:27 -0700 (PDT) Received: by 10.213.9.131 with SMTP id l3mr265977ebl.152.1334763086414; Wed, 18 Apr 2012 08:31:26 -0700 (PDT) Received: from eu1sys200aog108.obsmtp.com (eu1sys200aog108.obsmtp.com. [207.126.144.125]) by mx.google.com with SMTP id z4si7062546eem.80.2012.04.18.08.31.23 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 18 Apr 2012 08:31:26 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.125 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.125; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.125 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob108.postini.com ([207.126.147.11]) with SMTP ID DSNKT47eRnpluObHF7I0BWyZ6jfQEzNyXo4a@postini.com; Wed, 18 Apr 2012 15:31:26 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3299B188; Wed, 18 Apr 2012 15:30:58 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 94DEA2C8C; Wed, 18 Apr 2012 15:30:57 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 1E898A8081; Wed, 18 Apr 2012 17:30:51 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 18 Apr 2012 17:30:56 +0200 From: Linus Walleij To: Cc: Linus Walleij , Jamie Iles , Will Deacon , Grant Likely , Rob Herring , Russell King Subject: [PATCH 2/2] ARM: VIC: use the domain mapping function to assign handlers Date: Wed, 18 Apr 2012 17:30:54 +0200 Message-ID: <1334763054-19340-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.9.2 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnh8fy9cMrqFFbDuJlrGSEA/0l3URQu0DC5SuThKZRR4WLcRxYhoOqC7Ypb3A9nR6wHZKal From: Linus Walleij This removes the internal functions for assigning IRQ handlers to each interrupt in favor of using the internal map iterator in the irq domain code. Cc: Jamie Iles Cc: Will Deacon Cc: Grant Likely Cc: Rob Herring Cc: Russell King Signed-off-by: Linus Walleij --- arch/arm/common/vic.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index c558a3e..e0d5388 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -39,6 +39,7 @@ * struct vic_device - VIC PM device * @irq: The IRQ number for the base of the VIC. * @base: The register base for the VIC. + * @valid_sources: A bitmask of valid interrupts * @resume_sources: A bitmask of interrupts for resume. * @resume_irqs: The IRQs enabled for resume. * @int_select: Save for VIC_INT_SELECT. @@ -50,6 +51,7 @@ struct vic_device { void __iomem *base; int irq; + u32 valid_sources; u32 resume_sources; u32 resume_irqs; u32 int_select; @@ -164,6 +166,27 @@ static int __init vic_pm_init(void) late_initcall(vic_pm_init); #endif /* CONFIG_PM */ +static struct irq_chip vic_chip; + +static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct vic_device *v = d->host_data; + + /* Skip invalid IRQs, only register handlers for the real ones */ + if (!(v->valid_sources & (1 << hwirq))) + return -ENOTSUPP; + irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); + irq_set_chip_data(irq, v->base); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + return 0; +} + +static struct irq_domain_ops vic_irqdomain_ops = { + .map = vic_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + /** * vic_register() - Register a VIC. * @base: The base address of the VIC. @@ -191,6 +214,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq, v = &vic_devices[vic_id]; v->base = base; + v->valid_sources = valid_sources; v->resume_sources = resume_sources; v->irq = irq; vic_id++; @@ -289,23 +313,6 @@ static void __init vic_clear_interrupts(void __iomem *base) } } -static void __init vic_set_irq_sources(void __iomem *base, - unsigned int irq_start, u32 vic_sources) -{ - unsigned int i; - - for (i = 0; i < 32; i++) { - if (vic_sources & (1 << i)) { - unsigned int irq = irq_start + i; - - irq_set_chip_and_handler(irq, &vic_chip, - handle_level_irq); - irq_set_chip_data(irq, base); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } -} - /* * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. * The original cell has 32 interrupts, while the modified one has 64, @@ -340,7 +347,6 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, writel(32, base + VIC_PL190_DEF_VECT_ADDR); } - vic_set_irq_sources(base, irq_start, vic_sources); vic_register(base, irq_start, vic_sources, 0, node); } @@ -381,8 +387,6 @@ void __init __vic_init(void __iomem *base, unsigned int irq_start, vic_init2(base); - vic_set_irq_sources(base, irq_start, vic_sources); - vic_register(base, irq_start, vic_sources, resume_sources, node); }