From patchwork Wed Jun 20 12:56:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 9502 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EE71823E1B for ; Wed, 20 Jun 2012 12:57:27 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id B7465A1851B for ; Wed, 20 Jun 2012 12:57:27 +0000 (UTC) Received: by mail-gh0-f180.google.com with SMTP id z12so6026493ghb.11 for ; Wed, 20 Jun 2012 05:57:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=q2yj2iXNeLE0AbA2Dz05kCd5sjHqwJCxy8Uyyo5FikE=; b=UkiGQwMXW5Yu6JVOQYXPhGbtuXmkjW7iZmlZDhLkvLOi03UKd3Y1tvx429sesiFFLl j/QL2t/hlbWcWfsFCyDVWW37R50RSdAj5sg7Gmg8llRy84GxfoG45YpBZSAFT2QP4C2b ZdLGqYNTu/buEkDzyK2P2vOWUVqeC48QaFGnyywoA/Y6FkqtH4QqYs/XpbqYWkGojJWH j2p2Wwc39M7fNu57g+9OdbnAMUHpY69MI2GpJ0XQngXHydQyMjrfyv2zcb0qNQns1f3c 4A+DItam0zDfoPl4SmsU+FobMwjv0YE09qL/4+eVOIseWOOhBz/Cnz7THwQ+ACOXT3c7 /szw== Received: by 10.50.160.198 with SMTP id xm6mr4440123igb.0.1340197047359; Wed, 20 Jun 2012 05:57:27 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp178563ibb; Wed, 20 Jun 2012 05:57:26 -0700 (PDT) Received: by 10.180.24.68 with SMTP id s4mr11960955wif.4.1340197046299; Wed, 20 Jun 2012 05:57:26 -0700 (PDT) Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by mx.google.com with ESMTPS id e18si28888235wea.58.2012.06.20.05.57.25 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 20 Jun 2012 05:57:26 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=209.85.212.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) smtp.mail=lee.jones@linaro.org Received: by wibhn6 with SMTP id hn6so3387651wib.13 for ; Wed, 20 Jun 2012 05:57:25 -0700 (PDT) Received: by 10.180.103.42 with SMTP id ft10mr11878223wib.18.1340197045592; Wed, 20 Jun 2012 05:57:25 -0700 (PDT) Received: from localhost.localdomain (cpc1-aztw13-0-0-cust473.18-1.cable.virginmedia.com. [77.102.241.218]) by mx.google.com with ESMTPS id gc6sm38878374wib.0.2012.06.20.05.57.23 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 20 Jun 2012 05:57:24 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org Cc: linus.walleij@stericsson.com, arnd@arndb.de, grant.likely@secretlab.ca, linux@arm.linux.org.uk, broonie@opensource.wolfsonmicro.com, Lee Jones , Will Deacon Subject: [PATCH 15/15] ARM: perf: handle muxed CPU IRQ lines Date: Wed, 20 Jun 2012 13:56:51 +0100 Message-Id: <1340197011-5435-16-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1340197011-5435-1-git-send-email-lee.jones@linaro.org> References: <1340197011-5435-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQleeMG5uyHleKUoDtdYXZZ0fBAdYX09YonM5PAsEiQnD4g3jn6kAXSYpGDByfSXTZoK5ip+ When registering a PMU device, a platform can either use the generic IRQ handler, or supplement it with one of its own. One of the reasons a platform might choose to do this is to handle the case of muxed IRQ lines. If this is the case and the IRQ is handled on the wrong CPU, this patch sets affinity with the next successive online CPU. Cc: Will Deacon Signed-off-by: Lee Jones --- arch/arm/kernel/perf_event_v7.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index d3c5360..04a8867 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1069,8 +1069,18 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) /* * Did an overflow occur? */ - if (!armv7_pmnc_has_overflowed(pmnc)) + if (armv7_pmnc_has_overflowed(pmnc)) { + unsigned int next_cpu; + + next_cpu = cpumask_next(smp_processor_id(), cpu_online_mask); + + if (next_cpu >= nr_cpumask_bits) + next_cpu = cpumask_first(cpu_online_mask); + + irq_set_affinity(irq_num, cpumask_of(next_cpu)); + return IRQ_NONE; + } /* * Handle the counter(s) overflow(s)