From patchwork Mon Sep 24 14:43:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 11672 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 08BE823E42 for ; Mon, 24 Sep 2012 14:44:05 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 98788A18EC4 for ; Mon, 24 Sep 2012 14:44:04 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so10113591iej.11 for ; Mon, 24 Sep 2012 07:44:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=ZYRjeW9FyLfxcerep8bNbTnxl0GHYw33AoD1Y9RFphE=; b=EdBxuikterveUtGd/MiWhyXZ7Au5z4+yxMhKty0ZNN97mwOvfadMaZS7ysVfr4NluG p587kbvCbvqRkD+LHF2fEtRA7sDjQWjb2Oe72p2MNIhCb2/mdPDRjFTFaCDY0VusLsyv JgO6odno1kYDdOCDD709zDAJzutM1CSZSBcRAbn5lo656YjUILM7cl31yJ97jqL11r9a Y3ZxFlDUqgn7vqF9FvJNOc5qwZibnHB/R2kfmZnpHGfgKsLlg99+LCqGhsXOtZPOFDim /jOZ6a3jhRyqVGyZWiJWF5K02USQa6mOE1qFDv33eLlQ0qFjgI4PAW/vW31FmdzLzCyW iBaw== Received: by 10.50.237.41 with SMTP id uz9mr5407174igc.43.1348497844353; Mon, 24 Sep 2012 07:44:04 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp246561igc; Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received: by 10.14.202.131 with SMTP id d3mr15180798eeo.32.1348497843139; Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received: from eu1sys200aog112.obsmtp.com (eu1sys200aog112.obsmtp.com [207.126.144.133]) by mx.google.com with SMTP id 42si6844451eee.60.2012.09.24.07.43.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.133 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.133; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.133 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob112.postini.com ([207.126.147.11]) with SMTP ID DSNKUGBxqwooCjAziVzFzN4GmaYKs5Gtk8u3@postini.com; Mon, 24 Sep 2012 14:44:02 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3DD3812B; Mon, 24 Sep 2012 14:43:35 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8FDC8483A; Mon, 24 Sep 2012 14:43:33 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 7680E24C2C0; Mon, 24 Sep 2012 16:43:25 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 24 Sep 2012 16:43:33 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Cc: Linus Walleij , Lee Jones , Philippe Begnic , Srinidhi Kasagar , Ulf Hansson Subject: [PATCH 3/3] clk: ux500: Update sdmmc clock to 100MHz for u8500 Date: Mon, 24 Sep 2012 16:43:19 +0200 Message-ID: <1348497799-32143-4-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1348497799-32143-1-git-send-email-ulf.hansson@stericsson.com> References: <1348497799-32143-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkS/zaXx38O7Q4HyH2jLWQvbqUZJdtLg4TznZa95b/U3ywoBIirr6LkvneUctKCp03YKvzR From: Ulf Hansson For u8500 and using 100MHz as the frequency also requires the ape opp 100 voltage, thus use the prcmu_opp_volt_scalable clock type. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/u8500_clk.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index ca4a25e..7bebf1f 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -170,10 +170,11 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "mtu0"); clk_register_clkdev(clk, NULL, "mtu1"); - clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT); + clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, + 100000000, + CLK_IS_ROOT|CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdmmc"); - clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); clk_register_clkdev(clk, "dsihs2", "mcde");