From patchwork Thu Dec 20 18:53:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13680 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0385B23E02 for ; Thu, 20 Dec 2012 18:54:23 +0000 (UTC) Received: from mail-ia0-f175.google.com (mail-ia0-f175.google.com [209.85.210.175]) by fiordland.canonical.com (Postfix) with ESMTP id BEC2BA19062 for ; Thu, 20 Dec 2012 18:54:22 +0000 (UTC) Received: by mail-ia0-f175.google.com with SMTP id z3so3118938iad.20 for ; Thu, 20 Dec 2012 10:54:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :mime-version:content-type:x-gm-message-state; bh=MP2Qn3A8U0woEMhYEvHudlMx51OS+yIKAiTAVcP0czc=; b=La//BM+MwsP7oGva21XY0aQqqtoMe9rQR+OBIMRHwLNYQnQzLnn58S6kT/kidFPsjC 1XdQo6blQ5CXnY8xmjoYJsV6/8n19SKU0mcPbxH6eQIa6BmHRau5o8zYxknrxxmnLywP dY7NnBL5hphCXsRoP3XCnK4C6h+t0RUx3snWajU6cg7dRsKtkq7VxsJGbllKX+bLP6fL iJbJe8wS5TIxFp5YSsnbSELNzH/Ew1o2QPXJrp389vhrCw/rAI693ZHGePamqiBb2Bxs mui6fsbuWwLNKxXPAXRUHKpxJTS4BYQT8m4A7n9kal4sAnPLXrJNAXru03+PbqMQd8BA qEuw== X-Received: by 10.50.195.135 with SMTP id ie7mr11059507igc.8.1356029662218; Thu, 20 Dec 2012 10:54:22 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.115 with SMTP id m19csp49467igt; Thu, 20 Dec 2012 10:54:21 -0800 (PST) X-Received: by 10.14.2.66 with SMTP id 42mr25458271eee.7.1356029660999; Thu, 20 Dec 2012 10:54:20 -0800 (PST) Received: from eu1sys200aog109.obsmtp.com (eu1sys200aog109.obsmtp.com [207.126.144.127]) by mx.google.com with SMTP id l8si22059817eem.5.2012.12.20.10.54.02 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 20 Dec 2012 10:54:20 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.127 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.127; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.127 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob109.postini.com ([207.126.147.11]) with SMTP ID DSNKUNNex0gGj6h6Mb2qOhRMHXzD2H2S2cEU@postini.com; Thu, 20 Dec 2012 18:54:20 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 28457F3; Thu, 20 Dec 2012 18:53:49 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B9A04531B; Thu, 20 Dec 2012 18:53:49 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 4877AA8065; Thu, 20 Dec 2012 19:53:42 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 20 Dec 2012 19:53:48 +0100 From: Linus Walleij To: Cc: Anmar Oueja , Linus Walleij , Grant Likely , Russell King - ARM Linux Subject: [PATCH 1/2] ARM: versatile: bump IRQ numbers Date: Thu, 20 Dec 2012 19:53:41 +0100 Message-ID: <1356029621-30203-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnk6IcYiJRDJ8VA4vlivrt2GVxNKgI5zxFZL9RtIvQ0lutAQdnztIstu9hzcCHA9YVG3Sn+ From: Linus Walleij The Versatile starts to register Linux IRQ numbers from offset 0 which is illegal, since this is NO_IRQ. Bump all hard-coded IRQs by 32 to get rid of the problem. Cc: Grant Likely Cc: Russell King - ARM Linux Signed-off-by: Linus Walleij --- arch/arm/mach-versatile/include/mach/irqs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index bf44c61..0fd771c 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h @@ -25,7 +25,7 @@ * IRQ interrupts definitions are the same as the INT definitions * held within platform.h */ -#define IRQ_VIC_START 0 +#define IRQ_VIC_START 32 #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) @@ -100,7 +100,7 @@ /* * Secondary interrupt controller */ -#define IRQ_SIC_START 32 +#define IRQ_SIC_START 64 #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) @@ -120,7 +120,7 @@ #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) -#define IRQ_SIC_END 63 +#define IRQ_SIC_END 95 #define IRQ_GPIO0_START (IRQ_SIC_END + 1) #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)