From patchwork Tue Mar 12 17:08:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 15301 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DAC1A23E3E for ; Tue, 12 Mar 2013 17:09:53 +0000 (UTC) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7D009A18677 for ; Tue, 12 Mar 2013 17:09:53 +0000 (UTC) Received: by mail-ve0-f180.google.com with SMTP id jx10so59184veb.39 for ; Tue, 12 Mar 2013 10:09:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=69yZupdoJU8DO64IsmchMLFZFnZcQl3TOyeaaYX5iLQ=; b=GwLsnBa1PAE/XQmKLMyP8g9BqRtV7AE2HVsrTv2eEwjueuGvAqwb6BTuyLSj18IVoX Xy42/Rgf0NDKjYgrBPVm5ppU+t5G4BiMdNRtQWC29zxQb2LlUon/ylrXmI7hQvqrCfSj KjbDwm6RcAx9ypKD4CSCZQmPTU6tMZpREM2LkNyYw8SySpDcgVKkeW3xqsydFUjEkHUT 7zx05b3P0WXt4YdqPx77Q6mEGvQ+N9AfSEj5muUyFiTKlgyCXt2rOdJgPmucWYbstGLH 1NQFjc9NDMUGLFYy4OWTt3TSYiKsgqhGgRZqyVgikcnVfzM71lLOkdpHKCVjQqP3geEw hPGQ== X-Received: by 10.220.214.6 with SMTP id gy6mr3588516vcb.8.1363108192995; Tue, 12 Mar 2013 10:09:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp138430veb; Tue, 12 Mar 2013 10:09:52 -0700 (PDT) X-Received: by 10.60.21.165 with SMTP id w5mr12680612oee.109.1363108192311; Tue, 12 Mar 2013 10:09:52 -0700 (PDT) Received: from mail-ie0-x229.google.com (mail-ie0-x229.google.com [2607:f8b0:4001:c03::229]) by mx.google.com with ESMTPS id s7si20904197obw.166.2013.03.12.10.09.52 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Mar 2013 10:09:52 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:4001:c03::229 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=2607:f8b0:4001:c03::229; Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:4001:c03::229 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) smtp.mail=haojian.zhuang@linaro.org Received: by mail-ie0-f169.google.com with SMTP id 13so112856iea.0 for ; Tue, 12 Mar 2013 10:09:51 -0700 (PDT) X-Received: by 10.50.153.198 with SMTP id vi6mr12585222igb.112.1363108191740; Tue, 12 Mar 2013 10:09:51 -0700 (PDT) Received: from localhost.localdomain ([140.206.155.72]) by mx.google.com with ESMTPS id xc3sm20593825igb.10.2013.03.12.10.09.47 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Mar 2013 10:09:51 -0700 (PDT) From: Haojian Zhuang To: linux@arm.linux.org.uk, linus.walleij@linaro.org, arnd@arndb.de, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, pawel.moll@arm.com, swarren@nvidia.com, john.stultz@linaro.org, tglx@linutronix.de, mturquette@linaro.org Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v2 12/14] Document: append hisilicon clock binding Date: Wed, 13 Mar 2013 01:08:41 +0800 Message-Id: <1363108124-17484-13-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1363108124-17484-1-git-send-email-haojian.zhuang@linaro.org> References: <1363108124-17484-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQllfBBpcqZjM92IRA4m6g62nDXCF0UaPOYVeh3FdGBk0rbGKuJk1ZBXS8pJsj4GsyyNTGyM Add hisilicon clock binding document for device tree. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/clock/hisilicon.txt | 73 ++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt diff --git a/Documentation/devicetree/bindings/clock/hisilicon.txt b/Documentation/devicetree/bindings/clock/hisilicon.txt new file mode 100644 index 0000000..be8db9d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon.txt @@ -0,0 +1,73 @@ +Device Tree Clock bindings for arch-vt8500 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties for mux clocks: + - compatible : Shall be "hisilicon,hi3620-clk-mux". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-mux : array of mux register offset & mask bits + +Required properties for Hi3620 gate clocks: + - compatible : Shall be "hisilicon,hi3620-clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,hi3620-clkgate : array of enable register offset & enable bits + - hisilicon,hi3620-clkreset : array of reset register offset & enable bits + +Required properties for clock divider: + - compatible : Shall be "hisilicon,hi3620-clk-div". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - #hisilicon,clkdiv-table-cells : the number of parameters after phandle in + hisilicon,clkdiv-table property. + - hisilicon,clkdiv-table : list of value that are used to configure clock + divider. They're value of phandle, index & divider value. + - hisilicon,clkdiv : array of divider register offset & mask bits. + +Required properties for gate clocks: + - compatible : Shall be "hisilicon,clk-gate". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,clkgate-inverted : bool value. True means that set-to-disable. + +Required properties for clock fixed factor divider: + - compatible : Shall be "hisilicon,fixed-factor". + - clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. + - clock-output-names : shall be reference name. + - #clock-cells : from common clock binding; shall be set to 0. + - hisilicon,fixed-factor : array of multiplier & divider. + +For example: + timclk1: clkgate@38 { + compatible = "hisilicon,clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_timer1>; + clock-output-names = "timclk1"; + hisilicon,clkgate-inverted; + hisilicon,clkgate = <0 18>; + }; + + dtable: clkdiv@0 { + #hisilicon,clkdiv-table-cells = <2>; + }; + + div_cfgaxi: clkdiv@2 { + compatible = "hisilicon,hi3620-clk-div"; + #clock-cells = <0>; + clocks = <&div_shareaxi>; + clock-output-names = "cfgAXI_div"; + hisilicon,clkdiv-table = <&dtable 0x01 2>; + hisilicon,clkdiv = <0x100 0x60>; + };