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[86.16.136.251]) by mx.google.com with ESMTPS id j4sm20277893wiz.10.2013.04.08.08.23.33 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 08 Apr 2013 08:23:34 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, linus.walleij@stericsson.com, Lee Jones , Vinod Koul , Dan Williams , Per Forlin Subject: [PATCH 4/5] dmaengine: ste_dma40: Only configure a channel during a configure request Date: Mon, 8 Apr 2013 16:23:10 +0100 Message-Id: <1365434591-21569-4-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365434591-21569-1-git-send-email-lee.jones@linaro.org> References: <1365434591-21569-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQkebvhxVnKzXSo0L2b+FerPU0VHrmO1od01xRNHeAqq8k4xbB3cqFtIKUC8um3nGLlexeOh X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , According to the DMA documentation allocating a channel and configuring it are two separate actions. By moving the configuration code into the correct code path we lighten the burden on the information required to successfully allocate a channel. Cc: Vinod Koul Cc: Dan Williams Cc: Per Forlin Signed-off-by: Lee Jones --- drivers/dma/ste_dma40.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index ecca492..3543ea4 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2471,16 +2471,10 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) } pm_runtime_get_sync(d40c->base->dev); - /* Fill in basic CFG register values */ - d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, - &d40c->dst_def_cfg, chan_is_logical(d40c)); d40_set_prio_realtime(d40c); if (chan_is_logical(d40c)) { - d40_log_cfg(&d40c->dma_cfg, - &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) d40c->lcpa = d40c->base->lcpa_base + d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;