From patchwork Thu Apr 18 10:11:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 16205 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ye0-f198.google.com (mail-ye0-f198.google.com [209.85.213.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5AF3923974 for ; Thu, 18 Apr 2013 10:13:41 +0000 (UTC) Received: by mail-ye0-f198.google.com with SMTP id m12sf3745815yen.5 for ; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=7vsRLoj/JDzzsN8zsqXzRB0f9V2jt20H5Q10brQVabU=; b=o9D4xKGzzhCvBKgfTFa55D4qTKm1VMjnGaLAIUA39wtOXJYpRvjddJ9tmL34zCHDLu vEoQGMUHdi1JQdb3Z8g59087hdFk/VZIZsD7Cuha6UgzeCUYB65BBmtMnuDzrFCJnyuk +S/zjh3uwILNARaC56xvCPZ/LLVnfYSgYKRk00fuRmnWeuzCNrczIEcdUJ5WixCAwUjX qoKoXdYTO2de72h2CxeBB8ctVq6sB52SkDIfM2ZDPmnZEpdmosBnMqT2dJGzs0VAjwY8 Cc2Gxvy/B28eboftiDpznbm99PmSFjdc7RyZoboqBQhrptupAjBYxTenMek9VjIflOxc m9Ag== X-Received: by 10.236.82.46 with SMTP id n34mr5065806yhe.24.1366279984380; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.14.9 with SMTP id l9ls1405799qec.97.gmail; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) X-Received: by 10.220.91.17 with SMTP id k17mr7724727vcm.36.1366279984205; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) Received: from mail-vb0-x22d.google.com (mail-vb0-x22d.google.com [2607:f8b0:400c:c02::22d]) by mx.google.com with ESMTPS id gr6si6217932vdc.130.2013.04.18.03.13.04 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 03:13:04 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::22d is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::22d; Received: by mail-vb0-f45.google.com with SMTP id w15so2154429vbf.4 for ; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) X-Received: by 10.220.73.68 with SMTP id p4mr7740938vcj.41.1366279984065; Thu, 18 Apr 2013 03:13:04 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp115749veb; Thu, 18 Apr 2013 03:13:03 -0700 (PDT) X-Received: by 10.194.104.168 with SMTP id gf8mr17373969wjb.58.1366279983100; Thu, 18 Apr 2013 03:13:03 -0700 (PDT) Received: from mail-we0-x236.google.com (mail-we0-x236.google.com [2a00:1450:400c:c03::236]) by mx.google.com with ESMTPS id vy4si3437598wjc.62.2013.04.18.03.13.02 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 03:13:03 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c03::236 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=2a00:1450:400c:c03::236; Received: by mail-we0-f182.google.com with SMTP id m1so2071524wea.41 for ; Thu, 18 Apr 2013 03:13:02 -0700 (PDT) X-Received: by 10.194.82.34 with SMTP id f2mr1562063wjy.25.1366279982538; Thu, 18 Apr 2013 03:13:02 -0700 (PDT) Received: from localhost.localdomain (cpc34-aztw25-2-0-cust250.18-1.cable.virginmedia.com. [86.16.136.251]) by mx.google.com with ESMTPS id t7sm30483773wij.2.2013.04.18.03.13.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 03:13:01 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, linus.walleij@stericsson.com, Lee Jones , Vinod Koul , Dan Williams , Per Forlin , Rabin Vincent Subject: [PATCH 17/32] dmaengine: ste_dma40: Remove redundant argument from d40_phy_cfg() Date: Thu, 18 Apr 2013 11:11:59 +0100 Message-Id: <1366279934-30761-18-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1366279934-30761-1-git-send-email-lee.jones@linaro.org> References: <1366279934-30761-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQnP7gr18rajixfRuUoveSO+mwQVUHuwGOULW6AhMQ/lZuupVgw4+EvS6pdCacX6S8iV+2jU X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22d is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , d40_phy_cfg is now only ever called to configure physical channels, so there's no requirement to pass though an argument describing the type of channel and to subsequently test for it. Cc: Vinod Koul Cc: Dan Williams Cc: Per Forlin Cc: Rabin Vincent Signed-off-by: Lee Jones --- drivers/dma/ste_dma40.c | 3 +- drivers/dma/ste_dma40_ll.c | 101 +++++++++++++++++++++----------------------- drivers/dma/ste_dma40_ll.h | 3 +- 3 files changed, 50 insertions(+), 57 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 1c570b6..ff41972 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2799,8 +2799,7 @@ static int d40_set_runtime_config(struct dma_chan *chan, if (chan_is_logical(d40c)) d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); else - d40_phy_cfg(cfg, &d40c->src_def_cfg, - &d40c->dst_def_cfg, false); + d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg); /* These settings will take precedence later */ d40c->runtime_addr = config_addr; diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c index b72d3e2..9ab9dff 100644 --- a/drivers/dma/ste_dma40_ll.c +++ b/drivers/dma/ste_dma40_ll.c @@ -56,63 +56,58 @@ void d40_log_gim_unmask(u32 *src_cfg, u32 *dst_cfg) { *dst_cfg |= 1 << D40_SREG_CFG_LOG_GIM_POS; } -/* Sets up SRC and DST CFG register for both logical and physical channels */ -void d40_phy_cfg(struct stedma40_chan_cfg *cfg, - u32 *src_cfg, u32 *dst_cfg, bool is_log) +void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg) { u32 src = 0; u32 dst = 0; - if (!is_log) { - /* Physical channel */ - if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) || - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { - /* Set master port to 1 */ - src |= 1 << D40_SREG_CFG_MST_POS; - src |= D40_TYPE_TO_EVENT(cfg->dev_type); - - if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) - src |= 1 << D40_SREG_CFG_PHY_TM_POS; - else - src |= 3 << D40_SREG_CFG_PHY_TM_POS; - } - if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) || - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { - /* Set master port to 1 */ - dst |= 1 << D40_SREG_CFG_MST_POS; - dst |= D40_TYPE_TO_EVENT(cfg->dev_type); - - if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) - dst |= 1 << D40_SREG_CFG_PHY_TM_POS; - else - dst |= 3 << D40_SREG_CFG_PHY_TM_POS; - } - /* Interrupt on end of transfer for destination */ - dst |= 1 << D40_SREG_CFG_TIM_POS; - - /* Generate interrupt on error */ - src |= 1 << D40_SREG_CFG_EIM_POS; - dst |= 1 << D40_SREG_CFG_EIM_POS; - - /* PSIZE */ - if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) { - src |= 1 << D40_SREG_CFG_PHY_PEN_POS; - src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS; - } - if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { - dst |= 1 << D40_SREG_CFG_PHY_PEN_POS; - dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; - } - - /* Element size */ - src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; - dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; - - /* Set the priority bit to high for the physical channel */ - if (cfg->high_priority) { - src |= 1 << D40_SREG_CFG_PRI_POS; - dst |= 1 << D40_SREG_CFG_PRI_POS; - } + if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) || + (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { + /* Set master port to 1 */ + src |= 1 << D40_SREG_CFG_MST_POS; + src |= D40_TYPE_TO_EVENT(cfg->dev_type); + + if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) + src |= 1 << D40_SREG_CFG_PHY_TM_POS; + else + src |= 3 << D40_SREG_CFG_PHY_TM_POS; + } + if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) || + (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { + /* Set master port to 1 */ + dst |= 1 << D40_SREG_CFG_MST_POS; + dst |= D40_TYPE_TO_EVENT(cfg->dev_type); + + if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) + dst |= 1 << D40_SREG_CFG_PHY_TM_POS; + else + dst |= 3 << D40_SREG_CFG_PHY_TM_POS; + } + /* Interrupt on end of transfer for destination */ + dst |= 1 << D40_SREG_CFG_TIM_POS; + + /* Generate interrupt on error */ + src |= 1 << D40_SREG_CFG_EIM_POS; + dst |= 1 << D40_SREG_CFG_EIM_POS; + + /* PSIZE */ + if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) { + src |= 1 << D40_SREG_CFG_PHY_PEN_POS; + src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS; + } + if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { + dst |= 1 << D40_SREG_CFG_PHY_PEN_POS; + dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; + } + + /* Element size */ + src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; + dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; + + /* Set the priority bit to high for the physical channel */ + if (cfg->high_priority) { + src |= 1 << D40_SREG_CFG_PRI_POS; + dst |= 1 << D40_SREG_CFG_PRI_POS; } if (cfg->src_info.big_endian) diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index 8aad679..e54df09 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -434,8 +434,7 @@ void d40_log_gim_unmask(u32 *src_cfg, u32 *dst_cfg); void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, - u32 *dst_cfg, - bool is_log); + u32 *dst_cfg); void d40_log_cfg(struct stedma40_chan_cfg *cfg, u32 *lcsp1,