From patchwork Fri Oct 11 12:22:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Jindal X-Patchwork-Id: 20962 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f198.google.com (mail-ob0-f198.google.com [209.85.214.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1276125EA1 for ; Fri, 11 Oct 2013 12:23:11 +0000 (UTC) Received: by mail-ob0-f198.google.com with SMTP id va2sf16648214obc.5 for ; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=OWUZIeWDjFqFWT3TfsaNBea39202lCSUqRmRQMzAKoc=; b=NVJ3hMCFMysArmV/hFDIYllq3T7hhD5zbA4/psufK/54pGk+/GfJQ4QYp5igjuQsO/ AHQS6m7z+Z8284Gn+1ohLNS4UoaAvHteaauTsgX7r0i0ZFhlYOamKPWxDXZgPeg3yaoY Joo7GQ75azX+OTjNP7KJ009CxEH+YrRDiUpPZHQC04S/q5S0cTVm5yFgQ5gvLgIa5Glx yRj9YENjl3JJiPQs/+1HvSNKuqweAez5Qiiw3rzhbWupbZJGlG/BHu519adkOgtaeMKj pBVUST4P02MYMEASesd7txLR0jYXYhxq41aehXOi9BvrmNj4h3OEXKWl/vxbzrJsG5zA 1DCg== X-Received: by 10.50.129.42 with SMTP id nt10mr1511746igb.0.1381494190619; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.59.36 with SMTP id w4ls1303283qeq.67.gmail; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) X-Received: by 10.52.161.231 with SMTP id xv7mr17776631vdb.1.1381494190463; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) Received: from mail-vb0-f53.google.com (mail-vb0-f53.google.com [209.85.212.53]) by mx.google.com with ESMTPS id o5si16565344vdw.37.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Oct 2013 05:23:10 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.53; Received: by mail-vb0-f53.google.com with SMTP id i3so2645347vbh.26 for ; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) X-Gm-Message-State: ALoCoQlsRebUvRht2Yych8AucteL4BEb+hqCZvm/+AS/FBsRm4go3AxBKFHTmobMz76cacch1MeF X-Received: by 10.220.15.132 with SMTP id k4mr212372vca.45.1381494190341; Fri, 11 Oct 2013 05:23:10 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp34931vcz; Fri, 11 Oct 2013 05:23:09 -0700 (PDT) X-Received: by 10.66.235.106 with SMTP id ul10mr20967080pac.19.1381494189351; Fri, 11 Oct 2013 05:23:09 -0700 (PDT) Received: from mail-pd0-f176.google.com (mail-pd0-f176.google.com [209.85.192.176]) by mx.google.com with ESMTPS id fk10si39643482pab.203.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Oct 2013 05:23:09 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.176 is neither permitted nor denied by best guess record for domain of ankit.jindal@linaro.org) client-ip=209.85.192.176; Received: by mail-pd0-f176.google.com with SMTP id q10so4155878pdj.35 for ; Fri, 11 Oct 2013 05:23:08 -0700 (PDT) X-Received: by 10.66.234.193 with SMTP id ug1mr21540739pac.92.1381494188869; Fri, 11 Oct 2013 05:23:08 -0700 (PDT) Received: from pnqlab023.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id uw6sm59608947pbc.8.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Oct 2013 05:23:08 -0700 (PDT) From: Ankit Jindal To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, linaro-networking@linaro.org, linaro-kernel@lists.linaro.org, steve.mcintyre@linaro.org, tushar.jagad@linaro.org, catalin.marinas@arm.com, Ankit Jindal Subject: [RFC PATCH 3/4] ARM64: Big Endian fixes for kernel booting Date: Fri, 11 Oct 2013 17:52:14 +0530 Message-Id: <1381494135-15085-4-git-send-email-ankit.jindal@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381494135-15085-1-git-send-email-ankit.jindal@linaro.org> References: <1381494135-15085-1-git-send-email-ankit.jindal@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ankit.jindal@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , - Enable appropriate bits for big endian kernel in SYSCTLR.EL2 and SYSCTLR.EL1 registers - Swap entry point for secondary core for big endian kernel - Set machine type to "aarch64b" for big endian and "aarch64l" for little endian. Signed-off-by: Ankit Jindal Signed-off-by: Tushar Jagad --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/kernel/head.S | 34 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/setup.c | 19 +++++++++++++++---- arch/arm64/kernel/smp_spin_table.c | 5 +++-- arch/arm64/mm/proc.S | 2 +- 5 files changed, 60 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 5aceb83..473faf3 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -22,6 +22,13 @@ #include +/* Select code for any configuration running in BE mode */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define ARM_BE(code...) code +#else +#define ARM_BE(code...) +#endif + /* * Stack pushing/popping (register pairs only). Equivalent to store decrement * before, load increment after. diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 7090c12..45dc50d 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -122,6 +122,7 @@ .word 0 // reserved ENTRY(stext) + ARM_BE(bl setend_be) mov x21, x0 // x21=FDT bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET bl el2_setup // Drop to EL1 @@ -148,6 +149,34 @@ ENTRY(stext) ENDPROC(stext) /* + * Set el0-el1-el2 to Big endian + */ + +#if defined(CONFIG_CPU_BIG_ENDIAN) +ENTRY(setend_be) + mrs x21, CurrentEL + cmp x21, #PSR_MODE_EL2t + b.ne setend_be_el1_el0 + +setend_be_el2: + mrs x21, sctlr_el2 + mov x22, #(1<<25) + orr x21, x21, x22 + msr sctlr_el2, x21 + isb + +setend_be_el1_el0: + mrs x21, sctlr_el1 + mov x22, #(3<<24) + orr x21, x21, x22 + msr sctlr_el1, x21 + isb + + ret +ENDPROC(setend_be) +#endif /* defined(CONFIG_CPU_BIG_ENDIAN) */ + +/* * If we're fortunate enough to boot at EL2, ensure that the world is * sane before dropping to EL1. */ @@ -181,7 +210,11 @@ ENTRY(el2_setup) /* sctlr_el1 */ mov x0, #0x0800 // Set/clear RES{1,0} bits +#if defined(CONFIG_CPU_BIG_ENDIAN) + movk x0, #0x33d0, lsl #16 +#else movk x0, #0x30d0, lsl #16 +#endif msr sctlr_el1, x0 /* Coprocessor traps. */ @@ -235,6 +268,7 @@ ENTRY(__boot_cpu_mode) * cores are held until we're ready for them to initialise. */ ENTRY(secondary_holding_pen) + ARM_BE(bl setend_be) bl __calc_phys_offset // x24=phys offset bl el2_setup // Drop to EL1 mrs x0, mpidr_el1 diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 055cfb8..d47ae6d 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -64,6 +64,9 @@ static const char *cpu_name; static const char *machine_name; phys_addr_t __fdt_pointer __initdata; +static union { char c[8]; unsigned long l; } endian_test = { { 'l', '?', '?', '?', '?', '?', '?','b' } }; +#define ENDIANNESS ((char)endian_test.l) + /* * Standard memory resources */ @@ -117,8 +120,10 @@ static void __init setup_processor(void) printk("CPU: %s [%08x] revision %d\n", cpu_name, read_cpuid_id(), read_cpuid_id() & 15); - - sprintf(init_utsname()->machine, "aarch64"); + + snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", + "aarch64", ENDIANNESS); + elf_hwcap = 0; } @@ -310,9 +315,15 @@ static const char *hwcap_str[] = { static int c_show(struct seq_file *m, void *v) { int i; +#if 0 + int num = 1; + char c; + char *cptr = (char *)# + c = (*cptr) ? 'l' : 'b'; +#endif - seq_printf(m, "Processor\t: %s rev %d (%s)\n", - cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); + seq_printf(m, "Processor\t: %s rev %d (%s%c)\n", + cpu_name, read_cpuid_id() & 15, ELF_PLATFORM, ENDIANNESS); for_each_online_cpu(i) { /* diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c index 7c35fa6..7ad68bc 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c @@ -46,9 +46,10 @@ static int __init smp_spin_table_prepare_cpu(int cpu) if (!cpu_release_addr[cpu]) return -ENODEV; - + release_addr = __va(cpu_release_addr[cpu]); - release_addr[0] = (void *)__pa(secondary_holding_pen); + release_addr[0] = (void *)cpu_to_le64(__pa(secondary_holding_pen)); + __flush_dcache_area(release_addr, sizeof(release_addr[0])); /* diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index b1b31bb..380a707 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -166,5 +166,5 @@ ENDPROC(__cpu_setup) */ .type crval, #object crval: - .word 0x030802e2 // clear + .word 0x000802e2 // clear .word 0x0405d11d // set