From patchwork Sun Nov 17 04:30:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 21554 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f72.google.com (mail-qe0-f72.google.com [209.85.128.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BB6D223FBB for ; Sun, 17 Nov 2013 04:29:27 +0000 (UTC) Received: by mail-qe0-f72.google.com with SMTP id b4sf9959501qen.11 for ; Sat, 16 Nov 2013 20:29:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=T9EsFpRUX/+XbGmyQI8qvfgXp/IXNxsRvNn09Ea1trE=; b=VcMFKfysqslWmCX0MxfnutuR5XbZY4ThjkkHAdAsy9Nkse2IqjyMj8F9b4MMmcRphx t3Ep6hSDro4yAe9Hi1+nSMVEWTPtS+OFVI/XHOQaGWsi8/QzZnB3oK0MeRBqBjeE3cHc HBT48ivcTnUPDQhx5VZOD06CQuo+EZvfb1EFzxga8kRnaX8UOuqmzWiW0ONi2/6pR7d/ gORfRAksemJsOQsmGlq0dLC1ZC+xAA0O8W+RDhWwprmSEkawDSzWyZVrP8t5YU+LZzQ0 nGOOVeTHLE8mFqTf89ZNuAoTGd/ngC9YQlnX2rIeBOnHCV9HYeQGTUsn4QDxnLjFuOHh ovoA== X-Gm-Message-State: ALoCoQktXiQ9/ubUX4vDHcLdNPryp/2kX4/JNJXJxFTkGphEkJQjcx6lYtAk62DyAOS4mJM1OjAV X-Received: by 10.236.147.18 with SMTP id s18mr8623997yhj.28.1384662567603; Sat, 16 Nov 2013 20:29:27 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.83.72 with SMTP id o8ls2326703qey.0.gmail; Sat, 16 Nov 2013 20:29:27 -0800 (PST) X-Received: by 10.52.94.99 with SMTP id db3mr424936vdb.54.1384662567510; Sat, 16 Nov 2013 20:29:27 -0800 (PST) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id ud10si5075054vcb.66.2013.11.16.20.29.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 16 Nov 2013 20:29:27 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id oz11so4150697veb.3 for ; Sat, 16 Nov 2013 20:29:27 -0800 (PST) X-Received: by 10.52.249.3 with SMTP id yq3mr436807vdc.55.1384662567435; Sat, 16 Nov 2013 20:29:27 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp126857vcz; Sat, 16 Nov 2013 20:29:26 -0800 (PST) X-Received: by 10.66.2.234 with SMTP id 10mr14724616pax.39.1384662566459; Sat, 16 Nov 2013 20:29:26 -0800 (PST) Received: from mail-pd0-f170.google.com (mail-pd0-f170.google.com [209.85.192.170]) by mx.google.com with ESMTPS id yg5si6216622pbc.326.2013.11.16.20.29.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 16 Nov 2013 20:29:26 -0800 (PST) Received-SPF: neutral (google.com: 209.85.192.170 is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=209.85.192.170; Received: by mail-pd0-f170.google.com with SMTP id g10so826247pdj.29 for ; Sat, 16 Nov 2013 20:29:26 -0800 (PST) X-Received: by 10.68.233.201 with SMTP id ty9mr6899417pbc.72.1384662566040; Sat, 16 Nov 2013 20:29:26 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id ho3sm14498530pbb.23.2013.11.16.20.29.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 16 Nov 2013 20:29:25 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Christoffer Dall Subject: [PATCH v3 7/9] KVM: arm-vgic: Support unqueueing of LRs to the dist Date: Sat, 16 Nov 2013 20:30:18 -0800 Message-Id: <1384662620-13795-8-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1384662620-13795-1-git-send-email-christoffer.dall@linaro.org> References: <1384662620-13795-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , To properly access the VGIC state from user space it is very unpractical to have to loop through all the LRs in all register access functions. Instead, support moving all pending state from LRs to the distributor, but leave active state LRs alone. Note that to accurately present the active and pending state to VCPUs reading these distributor registers from a live VM, we would have to stop all other VPUs than the calling VCPU and ask each CPU to unqueue their LR state onto the distributor and add fields to track active state on the distributor side as well. We don't have any users of such functionality yet and there are other inaccuracies of the GIC emulation, so don't provide accurate synchronized access to this state just yet. However, when the time comes, having this function should help. Signed-off-by: Christoffer Dall Changelog[3]: - New patch in series --- virt/kvm/arm/vgic.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index ecf6dcf..44c669b 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -589,6 +589,72 @@ static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, return false; } +#define LR_CPUID(lr) \ + (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT) +#define LR_IRQID(lr) \ + ((lr) & GICH_LR_VIRTUALID) + +static void vgic_retire_lr(int lr_nr, int irq, struct vgic_cpu *vgic_cpu) +{ + clear_bit(lr_nr, vgic_cpu->lr_used); + vgic_cpu->vgic_lr[lr_nr] &= ~GICH_LR_STATE; + vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; +} + +/** + * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor + * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs + * + * Move any pending IRQs that have already been assigned to LRs back to the + * emulated distributor state so that the complete emulated state can be read + * from the main emulation structures without investigating the LRs. + * + * Note that IRQs in the active state in the LRs get their pending state moved + * to the distributor but the active state stays in the LRs, because we don't + * track the active state on the distributor side. + */ +static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + int vcpu_id = vcpu->vcpu_id; + int i, irq, source_cpu; + u32 *lr; + + for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { + lr = &vgic_cpu->vgic_lr[i]; + irq = LR_IRQID(*lr); + source_cpu = LR_CPUID(*lr); + + /* + * If the LR holds only an active interrupt (not pending) then + * just leave it alone. + */ + if (!__test_and_clear_bit(__ffs(GICH_LR_PENDING_BIT), + (unsigned long *)lr)) + continue; + + /* + * If the interrupt was only pending (not "active" or "pending + * and active") then we have effectively cleared the LR and it + * should be marked as free for other use. + */ + if (!(*lr & GICH_LR_STATE)) + vgic_retire_lr(i, irq, vgic_cpu); + + /* + * Finally, reestablish the pending state on the distributor + * and the CPU interface. It may have already been pending, + * but that is fine, then we are only setting a few bits that + * were already set. + */ + vgic_dist_irq_set(vcpu, irq); + if (irq < VGIC_NR_SGIS) + dist->irq_sgi_sources[vcpu_id][irq] |= 1 << source_cpu; + vgic_update_state(vcpu->kvm); + } +} + static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) @@ -848,8 +914,6 @@ static void vgic_update_state(struct kvm *kvm) } } -#define LR_CPUID(lr) \ - (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT) #define MK_LR_PEND(src, irq) \ (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq)) @@ -871,9 +935,7 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID; if (!vgic_irq_is_enabled(vcpu, irq)) { - vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; - clear_bit(lr, vgic_cpu->lr_used); - vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE; + vgic_retire_lr(lr, irq, vgic_cpu); if (vgic_irq_is_active(vcpu, irq)) vgic_irq_clear_active(vcpu, irq); } @@ -1664,6 +1726,14 @@ static int vgic_attr_regs_access(struct kvm_device *dev, } } + /* + * Move all pending IRQs from the LRs on all VCPUs so the pending + * state can be properly represented in the register state accessible + * through this API. + */ + kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) + vgic_unqueue_irqs(tmp_vcpu); + offset -= r->base; r->handle_mmio(vcpu, &mmio, offset); spin_unlock(&vgic->lock);