From patchwork Fri Nov 29 12:19:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 21882 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f197.google.com (mail-ie0-f197.google.com [209.85.223.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DB95923FC4 for ; Fri, 29 Nov 2013 12:20:22 +0000 (UTC) Received: by mail-ie0-f197.google.com with SMTP id e14sf31283053iej.8 for ; Fri, 29 Nov 2013 04:20:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=lye9464AcVCxeznmSYWgn1AJob7UcjYCBZFyzJkdAj0=; b=BXJIV43OAv8tEbyiJFEVzjuVO2ZYr2h6l4MB6IRF4um0uSgyTtBoGYTCZOrU0aTg3U Fo9nncWR0lLMdwFqzp1wgOUx+jtnWo068EqyArvyJe5cgWuIXshX5CTaV77+tUBLPGdQ WN7fq+z3cYnT9ZhUaAEEX3wiTOnFK5SNWFBt5mtR+t8TxnXHUj800Rlj8xGHMykhqpzA mlYcRloKikrwHJsly0oX/ZwfiLK110rHJnRpZkF5d08dyDi+aSeNT15C3bnkct3LowVD 2gY5MKGuYhrRFtp72TPC/Hi4yej+tGlwrkDkfkh7zkrN8Pzvm3Cp9TMj95rYIeXvGSHl pPHw== X-Gm-Message-State: ALoCoQmUQE94QBDTzyEE1NR49JXfQ6wY0G8jxtVxYoyTIlhKkQgiipWJxc5IbQgXNo1dyuTL4MBd X-Received: by 10.182.66.193 with SMTP id h1mr565941obt.47.1385727622582; Fri, 29 Nov 2013 04:20:22 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.73.69 with SMTP id j5ls142843qev.48.gmail; Fri, 29 Nov 2013 04:20:22 -0800 (PST) X-Received: by 10.220.173.134 with SMTP id p6mr1709896vcz.36.1385727622505; Fri, 29 Nov 2013 04:20:22 -0800 (PST) Received: from mail-vc0-f180.google.com (mail-vc0-f180.google.com [209.85.220.180]) by mx.google.com with ESMTPS id o7si24772576vcl.135.2013.11.29.04.20.22 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Nov 2013 04:20:22 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.180; Received: by mail-vc0-f180.google.com with SMTP id if17so6715777vcb.11 for ; Fri, 29 Nov 2013 04:20:22 -0800 (PST) X-Received: by 10.52.35.41 with SMTP id e9mr31336vdj.79.1385727622434; Fri, 29 Nov 2013 04:20:22 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp87446vcz; Fri, 29 Nov 2013 04:20:21 -0800 (PST) X-Received: by 10.236.29.106 with SMTP id h70mr1897539yha.98.1385727621889; Fri, 29 Nov 2013 04:20:21 -0800 (PST) Received: from mail-yh0-f48.google.com (mail-yh0-f48.google.com [209.85.213.48]) by mx.google.com with ESMTPS id y62si36487791yhc.44.2013.11.29.04.20.21 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Nov 2013 04:20:21 -0800 (PST) Received-SPF: neutral (google.com: 209.85.213.48 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=209.85.213.48; Received: by mail-yh0-f48.google.com with SMTP id f73so6605935yha.35 for ; Fri, 29 Nov 2013 04:20:21 -0800 (PST) X-Received: by 10.236.106.99 with SMTP id l63mr1945116yhg.81.1385727621700; Fri, 29 Nov 2013 04:20:21 -0800 (PST) Received: from localhost.localdomain (cpc15-aztw25-2-0-cust493.aztw.cable.virginm.net. [92.233.57.238]) by mx.google.com with ESMTPSA id m29sm101911689yho.14.2013.11.29.04.20.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Nov 2013 04:20:21 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dwmw2@infradead.org Cc: linus.walleij@linaro.org, linux-mtd@lists.infradead.org, angus.clark@st.com, Lee Jones Subject: [PATCH v3 24/36] mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-back Date: Fri, 29 Nov 2013 12:19:13 +0000 Message-Id: <1385727565-25794-25-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> References: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 77 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/devices/st_spi_fsm.h | 7 ++-- 2 files changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 3a6b233..2369da1 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -98,6 +98,8 @@ static struct seq_rw_config n25q_read4_configs[] = { {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; +static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ +static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ static struct stfsm_seq stfsm_seq_read_jedec = { @@ -439,6 +441,71 @@ static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, return 0; } +static int stfsm_n25q_config(struct stfsm *fsm) +{ + uint32_t flags = fsm->info->flags; + uint8_t vcr; + int ret = 0; + bool soc_reset; + + /* Configure 'READ' sequence */ + if (flags & FLASH_FLAG_32BIT_ADDR) + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read4_configs); + else + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read3_configs); + if (ret) { + dev_err(fsm->dev, + "failed to prepare READ sequence with flags [0x%08x]\n", + flags); + return ret; + } + + /* Configure 'WRITE' sequence (default configs) */ + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + default_write_configs); + if (ret) { + dev_err(fsm->dev, + "preparing WRITE sequence using flags [0x%08x] failed\n", + flags); + return ret; + } + + /* * Configure 'ERASE_SECTOR' sequence */ + stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); + + /* Configure 32-bit address support */ + if (flags & FLASH_FLAG_32BIT_ADDR) { + stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + + soc_reset = stfsm_can_handle_soc_reset(fsm); + if (soc_reset || !fsm->booted_from_spi) { + /* + * If we can handle SoC resets, we enable 32-bit + * address mode pervasively + */ + stfsm_enter_32bit_addr(fsm, 1); + } else { + /* + * If not, enable/disable for WRITE and ERASE + * operations (READ uses special commands) + */ + fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | + CFG_ERASESEC_TOGGLE_32BIT_ADDR); + } + } + + /* + * Configure device to use 8 dummy cycles + */ + vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | + N25Q_VCR_WRAP_CONT); + stfsm_wrvcr(fsm, vcr); + + return 0; +} + static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec) { const struct stfsm_seq *seq = &stfsm_seq_read_jedec; @@ -681,6 +748,16 @@ static int stfsm_probe(struct platform_device *pdev) fsm->info = info; + /* + * Configure READ/WRITE/ERASE sequences according to platform and + * device flags. + */ + if (info->config) { + ret = info->config(fsm); + if (ret) + return ret; + } + platform_set_drvdata(pdev, fsm); stfsm_fetch_platform_configs(pdev); diff --git a/drivers/mtd/devices/st_spi_fsm.h b/drivers/mtd/devices/st_spi_fsm.h index 6699174..b5ce07d 100644 --- a/drivers/mtd/devices/st_spi_fsm.h +++ b/drivers/mtd/devices/st_spi_fsm.h @@ -304,6 +304,8 @@ struct flash_info { int (*config)(struct stfsm *); }; +static int stfsm_n25q_config(struct stfsm *fsm); + static struct flash_info flash_types[] = { /* * ST Microelectronics/Numonyx -- @@ -347,9 +349,10 @@ static struct flash_info flash_types[] = { FLASH_FLAG_WRITE_1_2_2 | \ FLASH_FLAG_WRITE_1_1_4 | \ FLASH_FLAG_WRITE_1_4_4) - { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL }, + { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, + stfsm_n25q_config }, { "n25q256", 0x20ba19, 0, 64 * 1024, 512, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL }, + N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, /* * Spansion S25FLxxxP