From patchwork Thu Dec 12 19:55:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 22305 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f198.google.com (mail-ve0-f198.google.com [209.85.128.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 66BF223FC9 for ; Thu, 12 Dec 2013 19:54:19 +0000 (UTC) Received: by mail-ve0-f198.google.com with SMTP id oy12sf1911349veb.5 for ; Thu, 12 Dec 2013 11:54:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=V9ibW+EVHSKXr5qbm+8mFSDENKoA9jCd9cFKow5PLn8=; b=mWdWzDTLWgQOULfRegXVCFliRkzmvciYqxD1o3PVyXalxoJURR9NncmTS29pB0e60L S8Dfj2lWYlzYromAbR0//piXWMhm/0q9KbxB4rTtL/icDJrDclHmSfZ5/dHJ+Rg7YVA6 8zpwGHSBo9M79RCvWW1zlNfRjnmIW0DvlUAslPZzUjnliFWEjSP8iXdZTGi65H7XcpFC VrkYLjke5+GHdpPWBLomIMpmFJvp7XWwLHz89lquMTk9ZuZhkJCZHYFeD19E97U3+9nw Ncf2bPwVHLH00X20i2mW/nK1wpmq2VAF9MFK0rjx5j4hMnjSQfAiMJkV2V1kbSyV8Xno jwhg== X-Gm-Message-State: ALoCoQkat83kFRmkeCvh3bngvXf+2b6cZRXSkEab/f5Qt8OWwKitB9CRq/MpLDBVJ+UaicHqOMOF X-Received: by 10.58.39.202 with SMTP id r10mr3928104vek.12.1386878058885; Thu, 12 Dec 2013 11:54:18 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.128.41 with SMTP id nl9ls690218qeb.56.gmail; Thu, 12 Dec 2013 11:54:18 -0800 (PST) X-Received: by 10.220.17.131 with SMTP id s3mr4748971vca.20.1386878058792; Thu, 12 Dec 2013 11:54:18 -0800 (PST) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id tw10si8048336vec.6.2013.12.12.11.54.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Dec 2013 11:54:18 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id id10so650498vcb.33 for ; Thu, 12 Dec 2013 11:54:18 -0800 (PST) X-Received: by 10.52.165.131 with SMTP id yy3mr3924138vdb.25.1386878058706; Thu, 12 Dec 2013 11:54:18 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp381987vcz; Thu, 12 Dec 2013 11:54:18 -0800 (PST) X-Received: by 10.68.231.166 with SMTP id th6mr15067005pbc.27.1386878057867; Thu, 12 Dec 2013 11:54:17 -0800 (PST) Received: from mail-pb0-f51.google.com (mail-pb0-f51.google.com [209.85.160.51]) by mx.google.com with ESMTPS id qh6si1845325pbb.214.2013.12.12.11.54.17 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Dec 2013 11:54:17 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.51 is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=209.85.160.51; Received: by mail-pb0-f51.google.com with SMTP id up15so1117960pbc.10 for ; Thu, 12 Dec 2013 11:54:17 -0800 (PST) X-Received: by 10.68.218.3 with SMTP id pc3mr15245679pbc.71.1386878057461; Thu, 12 Dec 2013 11:54:17 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id ql10sm4014884pbc.44.2013.12.12.11.54.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Dec 2013 11:54:15 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linaro-kernel@lists.linaro.org, patches@linaro.org, Christoffer Dall , Thomas Gleixner Subject: [PATCH 04/10] irqchip: arm-gic: Define additional MMIO offsets and masks Date: Thu, 12 Dec 2013 11:55:43 -0800 Message-Id: <1386878149-13397-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1386878149-13397-1-git-send-email-christoffer.dall@linaro.org> References: <1386878149-13397-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- include/linux/irqchip/arm-gic.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index cac496b..0ceb389 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -17,6 +17,9 @@ #define GIC_CPU_EOI 0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -56,6 +59,15 @@ #define GICH_LR_ACTIVE_BIT (1 << 29) #define GICH_LR_EOI (1 << 19) +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT 27 +#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) + #define GICH_MISR_EOI (1 << 0) #define GICH_MISR_U (1 << 1)