From patchwork Tue Dec 17 05:29:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 22556 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f197.google.com (mail-pd0-f197.google.com [209.85.192.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D429A202E2 for ; Tue, 17 Dec 2013 05:30:25 +0000 (UTC) Received: by mail-pd0-f197.google.com with SMTP id v10sf17084158pde.8 for ; Mon, 16 Dec 2013 21:30:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=LEQhT38B3ApMgROWadIpP1hhe8Mqhc/PDDJHPAvRL3E=; b=ONOA+cWfGpQM27K4qsm0N21wwbRr6+Z87DOUPfrdcHIE1z/uaa1ElxHk+W5gZi9tVU nGvUqsFRWt7pvgRhKxBMCbOjmdp+B//5Db2fokL8p1n1g0nyU2zpy+IC6FIvaqS1UIH8 VbjKF1zjBpe//gUcoE6x4UXKWIbHkOos5gpl7u5QoMbQ5Pm4OEqTPxxu8Gh722QXAl0w vcL7DzyU8vyFUA6rF5H7b3BDUVyF+R1NUp5oZM4kdZ3p+ccax7IOQSJHXC9OlhqSNsgS OsHxaECbsIwnvYeXjFvsMSZxjP9WhPCj9l+Z2BRxG8JNyFyvspvFDeea5XFJ9a1PtpQB et7Q== X-Gm-Message-State: ALoCoQlhHlTROTv7d3YsVjklKNkaBETNUbGC6mw0tIRMiWy+i9dqmvjDwQBGAzCqaz/LmRPJOD0V X-Received: by 10.66.220.163 with SMTP id px3mr2881696pac.38.1387258225110; Mon, 16 Dec 2013 21:30:25 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.35.108 with SMTP id g12ls2358471qej.81.gmail; Mon, 16 Dec 2013 21:30:25 -0800 (PST) X-Received: by 10.58.254.200 with SMTP id ak8mr10084693ved.12.1387258224992; Mon, 16 Dec 2013 21:30:24 -0800 (PST) Received: from mail-vc0-f173.google.com (mail-vc0-f173.google.com [209.85.220.173]) by mx.google.com with ESMTPS id xw5si4568093vec.46.2013.12.16.21.30.24 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Dec 2013 21:30:24 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.173; Received: by mail-vc0-f173.google.com with SMTP id ia6so3910423vcb.32 for ; Mon, 16 Dec 2013 21:30:24 -0800 (PST) X-Received: by 10.52.230.102 with SMTP id sx6mr8352451vdc.15.1387258224910; Mon, 16 Dec 2013 21:30:24 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp44468vcz; Mon, 16 Dec 2013 21:30:24 -0800 (PST) X-Received: by 10.66.118.71 with SMTP id kk7mr24840915pab.14.1387258223587; Mon, 16 Dec 2013 21:30:23 -0800 (PST) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by mx.google.com with ESMTPS id xa2si10771355pab.84.2013.12.16.21.30.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Dec 2013 21:30:23 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.46 is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=209.85.220.46; Received: by mail-pa0-f46.google.com with SMTP id kl14so3929717pab.5 for ; Mon, 16 Dec 2013 21:30:23 -0800 (PST) X-Received: by 10.68.197.36 with SMTP id ir4mr24792341pbc.96.1387258223145; Mon, 16 Dec 2013 21:30:23 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id vn10sm30771688pbc.21.2013.12.16.21.30.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Dec 2013 21:30:22 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linaro-kernel@lists.linaro.org, patches@linaro.org, Christoffer Dall , Thomas Gleixner Subject: [PATCH v5 04/10] irqchip: arm-gic: Define additional MMIO offsets and masks Date: Mon, 16 Dec 2013 21:29:55 -0800 Message-Id: <1387258201-8738-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.5 In-Reply-To: <1387258201-8738-1-git-send-email-christoffer.dall@linaro.org> References: <1387258201-8738-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- include/linux/irqchip/arm-gic.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index cac496b..0ceb389 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -17,6 +17,9 @@ #define GIC_CPU_EOI 0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -56,6 +59,15 @@ #define GICH_LR_ACTIVE_BIT (1 << 29) #define GICH_LR_EOI (1 << 19) +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT 27 +#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) + #define GICH_MISR_EOI (1 << 0) #define GICH_MISR_U (1 << 1)