From patchwork Thu Jan 23 10:31:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 23595 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f72.google.com (mail-pb0-f72.google.com [209.85.160.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A508B218BD for ; Thu, 23 Jan 2014 10:32:44 +0000 (UTC) Received: by mail-pb0-f72.google.com with SMTP id up15sf3854407pbc.11 for ; Thu, 23 Jan 2014 02:32:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=nPC7yCMJJVi3CounU1Y0uQmhqu274isM/8Wh2fvfU1w=; b=giGwxL791rIODvzFWAFAJjDYvcYEbbX5wMDYYwVWjoWW4TnFT/B260lyqSqU6xvA1q sFqkNkR4xbDMX/AeJHfsVZk+Q93wFAIotK8WP+0rx92Y/g5r6i5l+dB+oBD6QJe4LRia JnsezpxT98rC4Vu3JGkDaSgUqCy3xIe2lNfLVgiG03Zt7w4iTzongjZJPq/MtDAf4AAp M7OlEkD+6wukgFiX6Ez8wFOFXMz8AdlwG+TX/+mJh5jhe9SIROEUsA/wfpHy65hycRIF rh9ZI9RLHvBndR5A5q9tyAfnBi3Mn728DpRa4d3R9SYZNeJ3p3GkhaBZgWoz5JdzwRX8 uM6g== X-Gm-Message-State: ALoCoQn4siGAgSAhCKI9yNwhzF1EKl0oIhmMVi7ezBM5IOtXuCNpxHHQEDdhX6l4Eo/SiTwWxevL X-Received: by 10.66.8.234 with SMTP id u10mr2842113paa.40.1390473163937; Thu, 23 Jan 2014 02:32:43 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.44.102 with SMTP id f93ls287490qga.75.gmail; Thu, 23 Jan 2014 02:32:43 -0800 (PST) X-Received: by 10.58.69.20 with SMTP id a20mr4220430veu.0.1390473163820; Thu, 23 Jan 2014 02:32:43 -0800 (PST) Received: from mail-vb0-f44.google.com (mail-vb0-f44.google.com [209.85.212.44]) by mx.google.com with ESMTPS id a15si6424447vew.83.2014.01.23.02.32.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Jan 2014 02:32:43 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.44; Received: by mail-vb0-f44.google.com with SMTP id f12so927315vbg.17 for ; Thu, 23 Jan 2014 02:32:43 -0800 (PST) X-Received: by 10.58.211.130 with SMTP id nc2mr4007458vec.7.1390473163752; Thu, 23 Jan 2014 02:32:43 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp15979vcz; Thu, 23 Jan 2014 02:32:43 -0800 (PST) X-Received: by 10.180.73.196 with SMTP id n4mr24034117wiv.24.1390473162484; Thu, 23 Jan 2014 02:32:42 -0800 (PST) Received: from mail-wg0-f48.google.com (mail-wg0-f48.google.com [74.125.82.48]) by mx.google.com with ESMTPS id k6si8773227wja.131.2014.01.23.02.32.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Jan 2014 02:32:42 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.48 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.48; Received: by mail-wg0-f48.google.com with SMTP id x13so1252751wgg.15 for ; Thu, 23 Jan 2014 02:32:42 -0800 (PST) X-Received: by 10.180.107.136 with SMTP id hc8mr24166370wib.11.1390473161944; Thu, 23 Jan 2014 02:32:41 -0800 (PST) Received: from localhost.localdomain ([80.76.198.141]) by mx.google.com with ESMTPSA id ay6sm21257831wjb.23.2014.01.23.02.32.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Jan 2014 02:32:41 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: linus.walleij@linaro.org, dwmw2@infradead.org, linux-mtd@lists.infradead.org, computersforpeace@gmail.com, Angus.Clark@st.com, DCG_UPD_stlinux_kernel@list.st.com, olivier.clergeaud@st.com, Lee Jones Subject: [PATCH RESEND v4 24/37] mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-back Date: Thu, 23 Jan 2014 10:31:12 +0000 Message-Id: <1390473085-24626-25-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> References: <1390473085-24626-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 3b56b6e..28d8ac0 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -310,6 +310,8 @@ struct flash_info { int (*config)(struct stfsm *); }; +static int stfsm_n25q_config(struct stfsm *fsm); + static struct flash_info flash_types[] = { /* * ST Microelectronics/Numonyx -- @@ -352,9 +354,10 @@ static struct flash_info flash_types[] = { FLASH_FLAG_WRITE_1_2_2 | \ FLASH_FLAG_WRITE_1_1_4 | \ FLASH_FLAG_WRITE_1_4_4) - { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL }, + { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, + stfsm_n25q_config }, { "n25q256", 0x20ba19, 0, 64 * 1024, 512, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL }, + N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, /* * Spansion S25FLxxxP @@ -491,6 +494,8 @@ static struct seq_rw_config n25q_read4_configs[] = { {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; +static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ +static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ static struct stfsm_seq stfsm_seq_read_jedec = { @@ -833,6 +838,71 @@ static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, return 0; } +static int stfsm_n25q_config(struct stfsm *fsm) +{ + uint32_t flags = fsm->info->flags; + uint8_t vcr; + int ret = 0; + bool soc_reset; + + /* Configure 'READ' sequence */ + if (flags & FLASH_FLAG_32BIT_ADDR) + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read4_configs); + else + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read3_configs); + if (ret) { + dev_err(fsm->dev, + "failed to prepare READ sequence with flags [0x%08x]\n", + flags); + return ret; + } + + /* Configure 'WRITE' sequence (default configs) */ + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + default_write_configs); + if (ret) { + dev_err(fsm->dev, + "preparing WRITE sequence using flags [0x%08x] failed\n", + flags); + return ret; + } + + /* * Configure 'ERASE_SECTOR' sequence */ + stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); + + /* Configure 32-bit address support */ + if (flags & FLASH_FLAG_32BIT_ADDR) { + stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + + soc_reset = stfsm_can_handle_soc_reset(fsm); + if (soc_reset || !fsm->booted_from_spi) { + /* + * If we can handle SoC resets, we enable 32-bit + * address mode pervasively + */ + stfsm_enter_32bit_addr(fsm, 1); + } else { + /* + * If not, enable/disable for WRITE and ERASE + * operations (READ uses special commands) + */ + fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | + CFG_ERASESEC_TOGGLE_32BIT_ADDR); + } + } + + /* + * Configure device to use 8 dummy cycles + */ + vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | + N25Q_VCR_WRAP_CONT); + stfsm_wrvcr(fsm, vcr); + + return 0; +} + static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec) { const struct stfsm_seq *seq = &stfsm_seq_read_jedec; @@ -1075,6 +1145,16 @@ static int stfsm_probe(struct platform_device *pdev) fsm->info = info; + /* + * Configure READ/WRITE/ERASE sequences according to platform and + * device flags. + */ + if (info->config) { + ret = info->config(fsm); + if (ret) + return ret; + } + platform_set_drvdata(pdev, fsm); stfsm_fetch_platform_configs(pdev);