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[209.132.180.67]) by mx.google.com with ESMTP id n8si8817065pab.29.2014.02.22.07.55.02; Sat, 22 Feb 2014 07:55:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751801AbaBVPyw (ORCPT + 9 others); Sat, 22 Feb 2014 10:54:52 -0500 Received: from mx1.redhat.com ([209.132.183.28]:11835 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751799AbaBVPyv (ORCPT ); Sat, 22 Feb 2014 10:54:51 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s1MFsIW7003488 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sat, 22 Feb 2014 10:54:18 -0500 Received: from shalem.localdomain.com (vpn1-6-222.ams2.redhat.com [10.36.6.222]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s1MFrjaE003748; Sat, 22 Feb 2014 10:54:15 -0500 From: Hans de Goede To: Tejun Heo , Maxime Ripard Cc: Oliver Schinagl , Richard Zhu , Roger Quadros , Lee Jones , linux-ide@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree , linux-sunxi@googlegroups.com, Balaji T K , Hans de Goede Subject: [PATCH v7 11/15] ata: ahci_platform: Manage SATA PHY Date: Sat, 22 Feb 2014 16:53:40 +0100 Message-Id: <1393084424-31099-12-git-send-email-hdegoede@redhat.com> In-Reply-To: <1393084424-31099-1-git-send-email-hdegoede@redhat.com> References: <1393084424-31099-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: hdegoede@redhat.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Roger Quadros Some platforms have a PHY hooked up to the SATA controller. The PHY needs to be initialized and powered up for SATA to work. We do that using the PHY framework. CC: Balaji T K Signed-off-by: Roger Quadros Signed-off-by: Hans de Goede --- drivers/ata/ahci.h | 2 ++ drivers/ata/ahci_platform.c | 47 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index bf8100c..3ab7ac9 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -37,6 +37,7 @@ #include #include +#include #include /* Enclosure Management Control */ @@ -325,6 +326,7 @@ struct ahci_host_priv { u32 em_msg_type; /* EM message type */ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ struct regulator *target_pwr; /* Optional */ + struct phy *phy; /* If platform uses phy */ void *plat_data; /* Other platform data */ /* * Optional ahci_start_engine override, if not set this gets set to the diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index d7e55ba..99d38c1 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "ahci.h" static void ahci_host_stop(struct ata_host *host); @@ -147,6 +148,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_clks); * the following order: * 1) Regulator * 2) Clocks (through ahci_platform_enable_clks) + * 3) Phy * * If resource enabling fails at any point the previous enabled * resources are disabled in reverse order. @@ -171,8 +173,23 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv) if (rc) goto disable_regulator; + if (hpriv->phy) { + rc = phy_init(hpriv->phy); + if (rc) + goto disable_clks; + + rc = phy_power_on(hpriv->phy); + if (rc) { + phy_exit(hpriv->phy); + goto disable_clks; + } + } + return 0; +disable_clks: + ahci_platform_disable_clks(hpriv); + disable_regulator: if (hpriv->target_pwr) regulator_disable(hpriv->target_pwr); @@ -186,14 +203,20 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources); * * This function disables all ahci_platform managed resources in * the following order: - * 1) Clocks (through ahci_platform_disable_clks) - * 2) Regulator + * 1) Phy + * 2) Clocks (through ahci_platform_disable_clks) + * 3) Regulator * * LOCKING: * None. */ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) { + if (hpriv->phy) { + phy_power_off(hpriv->phy); + phy_exit(hpriv->phy); + } + ahci_platform_disable_clks(hpriv); if (hpriv->target_pwr) @@ -222,6 +245,7 @@ static void ahci_platform_put_resources(struct device *dev, void *res) * 2) regulator for controlling the targets power (optional) * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node, * or for non devicetree enabled platforms a single clock + * 4) phy (optional) * * LOCKING: * None. @@ -283,6 +307,25 @@ struct ahci_host_priv *ahci_platform_get_resources( hpriv->clks[i] = clk; } + hpriv->phy = devm_phy_get(dev, "sata-phy"); + if (IS_ERR(hpriv->phy)) { + rc = PTR_ERR(hpriv->phy); + switch (rc) { + case -ENODEV: + case -ENOSYS: + /* continue normally */ + hpriv->phy = NULL; + break; + + case -EPROBE_DEFER: + goto err_out; + + default: + dev_err(dev, "couldn't get sata-phy\n"); + goto err_out; + } + } + devres_remove_group(dev, NULL); return hpriv;