From patchwork Thu Mar 20 09:20:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 26656 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f72.google.com (mail-qa0-f72.google.com [209.85.216.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 951AA202E0 for ; Thu, 20 Mar 2014 09:22:08 +0000 (UTC) Received: by mail-qa0-f72.google.com with SMTP id f11sf1287325qae.3 for ; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=z7qhaeZNf2FXMqnoEFBbfAbo4eMTlV33ff1AYOsDTjA=; b=FeHmTRCd0gFry3x2nL6qEyb/ztV5n59vp6S1baRz3Z3CzaDB4RAh1c5YWadJee3DlQ v3m1sfxtB45EUYbnQ8DPzzl9+4x6nVWj/L2BsKfgPBEmpsniBDw1pwys6PXJqk2JFt0h VGZPVT1Aaw44pITz2vi+UCQ0w4IZe20YgFZ1YzBjsFx4DPGwVu1QGTUDGPqhlaQePkSm VSO1ZnLTvKCD8QiuqFoetPmXI3v31QeMX5+tHDoDYouhlJNaunCMunijo0TcG0H8sSeR nsbOMVD0K1h1i7vSbqwtutg38IDH58ebk2C1uxWfd9xbrydM0Xn55izHs6hU8Gkoezme gEPw== X-Gm-Message-State: ALoCoQm7CQ73Ddh1pTcwMDOVjX99jbd7sWu51I9K6mhEf4E5FTWknA1EAZK/lNyhtAOQ9RjpRMGT X-Received: by 10.58.155.3 with SMTP id vs3mr7503734veb.16.1395307328409; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.107.198 with SMTP id h64ls178754qgf.84.gmail; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) X-Received: by 10.220.81.194 with SMTP id y2mr4149727vck.29.1395307328309; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id u5si307582vdo.22.2014.03.20.02.22.08 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:08 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id ld13so590472vcb.5 for ; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) X-Received: by 10.58.162.168 with SMTP id yb8mr12682522veb.9.1395307328221; Thu, 20 Mar 2014 02:22:08 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.78.9 with SMTP id i9csp372554vck; Thu, 20 Mar 2014 02:22:07 -0700 (PDT) X-Received: by 10.180.103.134 with SMTP id fw6mr22828341wib.8.1395307327054; Thu, 20 Mar 2014 02:22:07 -0700 (PDT) Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by mx.google.com with ESMTPS id x4si838409wjf.112.2014.03.20.02.22.06 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:07 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.169 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=209.85.212.169; Received: by mail-wi0-f169.google.com with SMTP id hm4so5790587wib.2 for ; Thu, 20 Mar 2014 02:22:06 -0700 (PDT) X-Received: by 10.194.78.173 with SMTP id c13mr33508124wjx.0.1395307326362; Thu, 20 Mar 2014 02:22:06 -0700 (PDT) Received: from lee--X1.home (host109-148-116-196.range109-148.btcentralplus.com. [109.148.116.196]) by mx.google.com with ESMTPSA id di9sm4735120wid.6.2014.03.20.02.22.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:05 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, computersforpeace@gmail.com Cc: linux-mtd@lists.infradead.org, dwmw2@infradead.org, Angus.Clark@st.com, Lee Jones Subject: [PATCH v6 23/36] mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-back Date: Thu, 20 Mar 2014 09:20:55 +0000 Message-Id: <1395307268-12721-24-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> References: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Acked-by Angus Clark Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index c902d5b..b4d2a18 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -312,6 +312,8 @@ struct flash_info { int (*config)(struct stfsm *); }; +static int stfsm_n25q_config(struct stfsm *fsm); + static struct flash_info flash_types[] = { /* * ST Microelectronics/Numonyx -- @@ -354,9 +356,10 @@ static struct flash_info flash_types[] = { FLASH_FLAG_WRITE_1_2_2 | \ FLASH_FLAG_WRITE_1_1_4 | \ FLASH_FLAG_WRITE_1_4_4) - { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL }, + { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, + stfsm_n25q_config }, { "n25q256", 0x20ba19, 0, 64 * 1024, 512, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL }, + N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, /* * Spansion S25FLxxxP @@ -493,6 +496,8 @@ static struct seq_rw_config n25q_read4_configs[] = { {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; +static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ +static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ static struct stfsm_seq stfsm_seq_read_jedec = { @@ -840,6 +845,71 @@ static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, return 0; } +static int stfsm_n25q_config(struct stfsm *fsm) +{ + uint32_t flags = fsm->info->flags; + uint8_t vcr; + int ret = 0; + bool soc_reset; + + /* Configure 'READ' sequence */ + if (flags & FLASH_FLAG_32BIT_ADDR) + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read4_configs); + else + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read3_configs); + if (ret) { + dev_err(fsm->dev, + "failed to prepare READ sequence with flags [0x%08x]\n", + flags); + return ret; + } + + /* Configure 'WRITE' sequence (default configs) */ + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + default_write_configs); + if (ret) { + dev_err(fsm->dev, + "preparing WRITE sequence using flags [0x%08x] failed\n", + flags); + return ret; + } + + /* * Configure 'ERASE_SECTOR' sequence */ + stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); + + /* Configure 32-bit address support */ + if (flags & FLASH_FLAG_32BIT_ADDR) { + stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + + soc_reset = stfsm_can_handle_soc_reset(fsm); + if (soc_reset || !fsm->booted_from_spi) { + /* + * If we can handle SoC resets, we enable 32-bit + * address mode pervasively + */ + stfsm_enter_32bit_addr(fsm, 1); + } else { + /* + * If not, enable/disable for WRITE and ERASE + * operations (READ uses special commands) + */ + fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | + CFG_ERASESEC_TOGGLE_32BIT_ADDR); + } + } + + /* + * Configure device to use 8 dummy cycles + */ + vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | + N25Q_VCR_WRAP_CONT); + stfsm_wrvcr(fsm, vcr); + + return 0; +} + static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec) { const struct stfsm_seq *seq = &stfsm_seq_read_jedec; @@ -1073,6 +1143,16 @@ static int stfsm_probe(struct platform_device *pdev) if (info->sector_size * info->n_sectors > 0x1000000) info->flags |= FLASH_FLAG_32BIT_ADDR; + /* + * Configure READ/WRITE/ERASE sequences according to platform and + * device flags. + */ + if (info->config) { + ret = info->config(fsm); + if (ret) + return ret; + } + fsm->mtd.dev.parent = &pdev->dev; fsm->mtd.type = MTD_NORFLASH; fsm->mtd.writesize = 4;