From patchwork Thu Mar 20 09:21:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 26667 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f69.google.com (mail-oa0-f69.google.com [209.85.219.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1C648202E0 for ; Thu, 20 Mar 2014 09:22:32 +0000 (UTC) Received: by mail-oa0-f69.google.com with SMTP id i7sf2418409oag.4 for ; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=UT+e3v3vDcmZ7i5o8SJ5d3RMYEHfTRysLwPCZOM3Haw=; b=mZOXQpj+QMrEjU1zDxZGDtqUPQ1qyo2sdhv3VqV3qBO12PR2Zw6J7pv66aC94eRLLs ZpLxR6SHNQQSsLW4lxZjnL2zhh+bBaE9ruj24pWRFo8W7NPvXlONp+7iwUngcEuH+zP1 AVC3kfZn038c3MqO50QPGkA0EJbU4qDPXr95tF4izTJ7VzFjNeRdMP0hwcVAS2JwPRbw DckTaKRmzWpTRcjr1zbHekV7N3FTyu2/NmAbQTgWfywUO0qZ1mwnAicHzMuRzq6RYVdd Iug8CRyb9e0HqRh1JYTsSo5B6FX4SZt5xlL4PQqH8OtBsqU5ypVrQVF5XW4FKvv4yIis SWiA== X-Gm-Message-State: ALoCoQnYVh2xqtO/WsnGZnG0jMi8d87pJqkslSWLL7uA9GQe/SuXkzG7LE0YIOsH5uikD8pPkkJA X-Received: by 10.182.60.37 with SMTP id e5mr3120613obr.30.1395307352501; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.92.85 with SMTP id a79ls149086qge.72.gmail; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) X-Received: by 10.220.192.71 with SMTP id dp7mr41901vcb.45.1395307352304; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id sv2si301074vdc.111.2014.03.20.02.22.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:32 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id ld13so599472vcb.33 for ; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) X-Received: by 10.220.192.71 with SMTP id dp7mr41895vcb.45.1395307352203; Thu, 20 Mar 2014 02:22:32 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.78.9 with SMTP id i9csp372593vck; Thu, 20 Mar 2014 02:22:31 -0700 (PDT) X-Received: by 10.180.96.200 with SMTP id du8mr1695063wib.43.1395307350873; Thu, 20 Mar 2014 02:22:30 -0700 (PDT) Received: from mail-wg0-f42.google.com (mail-wg0-f42.google.com [74.125.82.42]) by mx.google.com with ESMTPS id fu5si1125884wib.51.2014.03.20.02.22.30 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:30 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.42; Received: by mail-wg0-f42.google.com with SMTP id y10so362446wgg.13 for ; Thu, 20 Mar 2014 02:22:30 -0700 (PDT) X-Received: by 10.194.236.232 with SMTP id ux8mr7020171wjc.46.1395307350158; Thu, 20 Mar 2014 02:22:30 -0700 (PDT) Received: from lee--X1.home (host109-148-116-196.range109-148.btcentralplus.com. [109.148.116.196]) by mx.google.com with ESMTPSA id di9sm4735120wid.6.2014.03.20.02.22.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 02:22:28 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, computersforpeace@gmail.com Cc: linux-mtd@lists.infradead.org, dwmw2@infradead.org, Angus.Clark@st.com, Lee Jones Subject: [PATCH v6 34/36] mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct Date: Thu, 20 Mar 2014 09:21:06 +0000 Message-Id: <1395307268-12721-35-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> References: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris Acked-by Angus Clark Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 64 ++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index dc9412a..dccbac0 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -273,6 +273,19 @@ #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 +struct stfsm_seq { + uint32_t data_size; + uint32_t addr1; + uint32_t addr2; + uint32_t addr_cfg; + uint32_t seq_opc[5]; + uint32_t mode; + uint32_t dummy; + uint32_t status; + uint8_t seq[16]; + uint32_t seq_cfg; +} __packed __aligned(4); + struct stfsm { struct device *dev; void __iomem *base; @@ -286,20 +299,11 @@ struct stfsm { bool booted_from_spi; bool reset_signal; bool reset_por; -}; -struct stfsm_seq { - uint32_t data_size; - uint32_t addr1; - uint32_t addr2; - uint32_t addr_cfg; - uint32_t seq_opc[5]; - uint32_t mode; - uint32_t dummy; - uint32_t status; - uint8_t seq[16]; - uint32_t seq_cfg; -} __packed __aligned(4); + struct stfsm_seq stfsm_seq_read; + struct stfsm_seq stfsm_seq_write; + struct stfsm_seq stfsm_seq_en_32bit_addr; +}; /* Parameters to configure a READ or WRITE FSM sequence */ struct seq_rw_config { @@ -587,10 +591,6 @@ static struct seq_rw_config stfsm_s25fl_write4_configs[] = { */ #define W25Q_STATUS_QE (0x1 << 9) -static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ -static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ -static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ - static struct stfsm_seq stfsm_seq_read_jedec = { .data_size = TRANSFER_SIZE(8), .seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -826,7 +826,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { - struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr; + struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; seq->seq_opc[0] = (SEQ_OPC_PADS_1 | @@ -1101,7 +1101,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) int ret; /* Configure 'READ' sequence */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, default_read_configs); if (ret) { dev_err(fsm->dev, @@ -1111,7 +1111,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) } /* Configure 'WRITE' sequence */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, default_write_configs); if (ret) { dev_err(fsm->dev, @@ -1146,7 +1146,7 @@ static int stfsm_mx25_config(struct stfsm *fsm) */ if (flags & FLASH_FLAG_32BIT_ADDR) { /* Configure 'enter_32bitaddr' FSM sequence */ - stfsm_mx25_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); soc_reset = stfsm_can_handle_soc_reset(fsm); if (soc_reset || !fsm->booted_from_spi) { @@ -1169,7 +1169,7 @@ static int stfsm_mx25_config(struct stfsm *fsm) } /* For QUAD mode, set 'QE' STATUS bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta); sta |= MX25_STATUS_QE; @@ -1188,10 +1188,10 @@ static int stfsm_n25q_config(struct stfsm *fsm) /* Configure 'READ' sequence */ if (flags & FLASH_FLAG_32BIT_ADDR) - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, n25q_read4_configs); else - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, n25q_read3_configs); if (ret) { dev_err(fsm->dev, @@ -1201,7 +1201,7 @@ static int stfsm_n25q_config(struct stfsm *fsm) } /* Configure 'WRITE' sequence (default configs) */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, default_write_configs); if (ret) { dev_err(fsm->dev, @@ -1215,7 +1215,7 @@ static int stfsm_n25q_config(struct stfsm *fsm) /* Configure 32-bit address support */ if (flags & FLASH_FLAG_32BIT_ADDR) { - stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); soc_reset = stfsm_can_handle_soc_reset(fsm); if (soc_reset || !fsm->booted_from_spi) { @@ -1374,12 +1374,12 @@ static int stfsm_s25fl_config(struct stfsm *fsm) * Prepare Read/Write/Erase sequences according to S25FLxxx * 32-bit address command set */ - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, stfsm_s25fl_read4_configs); if (ret) return ret; - ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, stfsm_s25fl_write4_configs); if (ret) return ret; @@ -1415,7 +1415,7 @@ static int stfsm_s25fl_config(struct stfsm *fsm) } /* Check status of 'QE' bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1); if (data_pads == 4) { if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { @@ -1465,7 +1465,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) return ret; /* If using QUAD mode, set QE STATUS bit */ - data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; + data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; if (data_pads == 4) { stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta1); stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sta2); @@ -1485,7 +1485,7 @@ static int stfsm_w25q_config(struct stfsm *fsm) static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, uint32_t offset) { - struct stfsm_seq *seq = &stfsm_seq_read; + struct stfsm_seq *seq = &fsm->stfsm_seq_read; uint32_t data_pads; uint32_t read_mask; uint32_t size_ub; @@ -1546,7 +1546,7 @@ static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, static int stfsm_write(struct stfsm *fsm, const uint8_t *const buf, const uint32_t size, const uint32_t offset) { - struct stfsm_seq *seq = &stfsm_seq_write; + struct stfsm_seq *seq = &fsm->stfsm_seq_write; uint32_t data_pads; uint32_t write_mask; uint32_t size_ub;