From patchwork Mon Apr 21 21:11:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 28726 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f197.google.com (mail-qc0-f197.google.com [209.85.216.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2277620341 for ; Mon, 21 Apr 2014 21:12:56 +0000 (UTC) Received: by mail-qc0-f197.google.com with SMTP id i8sf21116706qcq.0 for ; Mon, 21 Apr 2014 14:12:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=dhuid/hrdN60VH0XmREqp6VbV0W8amtAf9PP3wBFDY0=; b=QQ62VlHrklSUYn4t+jp2ybHsxGX//3cDIIhyYUdjRasaaMQxPsUFIuLRO5M2px34iy w26d5YALzyrAWl+NTsOOq8JM0FsYLq6lD4O9HldDW+VkOQp/gBYTMD0nBQ7WqvwpjfCV DELIueNJQDeVBsxBxuU9Kk5wgyq2DFDtJqGo8mFl/p5Kjfkg6q8ObJTm7NdKOKWtkFR0 DgJm732l6jO1OFzHPEHsdC0CnWi4jK1djgMZnAD31leL+RtEkbudBZrb4eS1c4RnKikn ps0fZNACwrhLnJ/Hx+rBZDhVc3ZiLhKj9qvmEDqY/yoWjPqsPJWoRaRh/ZIxHoUVJmcC onoA== X-Gm-Message-State: ALoCoQkXZI7qcwVRlLV3JKpIt7BCQ3XorJRft7nWGHUxik/YgU2sVcE6C/o03K5YKB5NUavC8/01 X-Received: by 10.236.29.51 with SMTP id h39mr17595026yha.45.1398114776075; Mon, 21 Apr 2014 14:12:56 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.93.131 with SMTP id d3ls506946qge.52.gmail; Mon, 21 Apr 2014 14:12:55 -0700 (PDT) X-Received: by 10.221.55.133 with SMTP id vy5mr31846911vcb.17.1398114775913; Mon, 21 Apr 2014 14:12:55 -0700 (PDT) Received: from mail-ve0-f181.google.com (mail-ve0-f181.google.com [209.85.128.181]) by mx.google.com with ESMTPS id fn10si6431475vdc.153.2014.04.21.14.12.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 21 Apr 2014 14:12:55 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.181; Received: by mail-ve0-f181.google.com with SMTP id oy12so8314611veb.26 for ; Mon, 21 Apr 2014 14:12:55 -0700 (PDT) X-Received: by 10.220.190.197 with SMTP id dj5mr31745420vcb.19.1398114775784; Mon, 21 Apr 2014 14:12:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp318818vcb; Mon, 21 Apr 2014 14:12:55 -0700 (PDT) X-Received: by 10.68.204.162 with SMTP id kz2mr40440311pbc.13.1398114774839; Mon, 21 Apr 2014 14:12:54 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id sr9si21463668pab.489.2014.04.21.14.12.53; Mon, 21 Apr 2014 14:12:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754763AbaDUVMf (ORCPT + 26 others); Mon, 21 Apr 2014 17:12:35 -0400 Received: from mail-yh0-f44.google.com ([209.85.213.44]:35741 "EHLO mail-yh0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754473AbaDUVMV (ORCPT ); Mon, 21 Apr 2014 17:12:21 -0400 Received: by mail-yh0-f44.google.com with SMTP id f10so4028929yha.17 for ; Mon, 21 Apr 2014 14:12:20 -0700 (PDT) X-Received: by 10.236.0.200 with SMTP id 48mr19830553yhb.72.1398114740745; Mon, 21 Apr 2014 14:12:20 -0700 (PDT) Received: from localhost.localdomain (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id d68sm73391492yhc.37.2014.04.21.14.12.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Apr 2014 14:12:20 -0700 (PDT) From: Alex Elder To: mturquette@linaro.org, mporter@linaro.org, bcm@fixthebug.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 RESEND 7/7] clk: bcm281xx: add clock hysteresis support Date: Mon, 21 Apr 2014 16:11:43 -0500 Message-Id: <1398114703-32410-8-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1398114703-32410-1-git-send-email-elder@linaro.org> References: <1398114703-32410-1-git-send-email-elder@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: elder@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for clock gate hysteresis control. For now, if it's defined for a clock, it's enabled. Signed-off-by: Alex Elder --- drivers/clk/bcm/clk-kona-setup.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/bcm/clk-kona.c | 33 +++++++++++++++++++++++++++++++++ drivers/clk/bcm/clk-kona.h | 19 +++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index 773ad7c..e5aeded 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -81,6 +81,7 @@ static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk) struct peri_clk_data *peri; struct bcm_clk_policy *policy; struct bcm_clk_gate *gate; + struct bcm_clk_hyst *hyst; struct bcm_clk_div *div; struct bcm_clk_sel *sel; struct bcm_clk_trig *trig; @@ -106,12 +107,25 @@ static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk) } gate = &peri->gate; + hyst = &peri->hyst; if (gate_exists(gate)) { if (gate->offset > limit) { pr_err("%s: bad gate offset for %s (%u > %u)\n", __func__, name, gate->offset, limit); return false; } + + if (hyst_exists(hyst)) { + if (hyst->offset > limit) { + pr_err("%s: bad hysteresis offset for %s " + "(%u > %u)\n", __func__, + name, hyst->offset, limit); + return false; + } + } + } else if (hyst_exists(hyst)) { + pr_err("%s: hysteresis but no gate for %s\n", __func__, name); + return false; } div = &peri->div; @@ -261,6 +275,17 @@ static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name, return true; } +static bool hyst_valid(struct bcm_clk_hyst *hyst, const char *clock_name) +{ + if (!bit_posn_valid(hyst->en_bit, "hysteresis enable", clock_name)) + return false; + + if (!bit_posn_valid(hyst->val_bit, "hysteresis value", clock_name)) + return false; + + return true; +} + /* * A selector bitfield must be valid. Its parent_sel array must * also be reasonable for the field. @@ -379,6 +404,7 @@ peri_clk_data_valid(struct kona_clk *bcm_clk) struct peri_clk_data *peri; struct bcm_clk_policy *policy; struct bcm_clk_gate *gate; + struct bcm_clk_hyst *hyst; struct bcm_clk_sel *sel; struct bcm_clk_div *div; struct bcm_clk_div *pre_div; @@ -406,6 +432,10 @@ peri_clk_data_valid(struct kona_clk *bcm_clk) if (gate_exists(gate) && !gate_valid(gate, "gate", name)) return false; + hyst = &peri->hyst; + if (hyst_exists(hyst) && !hyst_valid(hyst, name)) + return false; + sel = &peri->sel; if (selector_exists(sel)) { if (!sel_valid(sel, "selector", name)) diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c index 7d90c34..d603c4e 100644 --- a/drivers/clk/bcm/clk-kona.c +++ b/drivers/clk/bcm/clk-kona.c @@ -527,6 +527,35 @@ static int clk_gate(struct ccu_data *ccu, const char *name, return -EIO; } +/* Hysteresis operations */ + +/* + * If a clock gate requires a turn-off delay it will have + * "hysteresis" register bits defined. The first, if set, enables + * the delay; and if enabled, the second bit determines whether the + * delay is "low" or "high" (1 means high). For now, if it's + * defined for a clock, we set it. + */ +static bool hyst_init(struct ccu_data *ccu, struct bcm_clk_hyst *hyst) +{ + u32 offset; + u32 reg_val; + u32 mask; + + if (!hyst_exists(hyst)) + return true; + + offset = hyst->offset; + mask = (u32)1 << hyst->en_bit; + mask |= (u32)1 << hyst->val_bit; + + reg_val = __ccu_read(ccu, offset); + reg_val |= mask; + __ccu_write(ccu, offset, reg_val); + + return true; +} + /* Trigger operations */ /* @@ -1131,6 +1160,10 @@ static bool __peri_clk_init(struct kona_clk *bcm_clk) pr_err("%s: error initializing gate for %s\n", __func__, name); return false; } + if (!hyst_init(ccu, &peri->hyst)) { + pr_err("%s: error initializing hyst for %s\n", __func__, name); + return false; + } if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) { pr_err("%s: error initializing divider for %s\n", __func__, name); diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h index 4bcba13..2537b30 100644 --- a/drivers/clk/bcm/clk-kona.h +++ b/drivers/clk/bcm/clk-kona.h @@ -60,6 +60,8 @@ #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) +#define hyst_exists(hyst) ((hyst)->offset != 0) + #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) #define divider_has_fraction(div) (!divider_is_fixed(div) && \ @@ -205,6 +207,22 @@ struct bcm_clk_gate { .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ } +/* Gate hysteresis for clocks */ +struct bcm_clk_hyst { + u32 offset; /* hyst register offset (normally CLKGATE) */ + u32 en_bit; /* bit used to enable hysteresis */ + u32 val_bit; /* if enabled: 0 = low delay; 1 = high delay */ +}; + +/* Hysteresis initialization macro */ + +#define HYST(_offset, _en_bit, _val_bit) \ + { \ + .offset = (_offset), \ + .en_bit = (_en_bit), \ + .val_bit = (_val_bit), \ + } + /* * Each clock can have zero, one, or two dividers which change the * output rate of the clock. Each divider can be either fixed or @@ -372,6 +390,7 @@ struct bcm_clk_trig { struct peri_clk_data { struct bcm_clk_policy policy; struct bcm_clk_gate gate; + struct bcm_clk_hyst hyst; struct bcm_clk_trig pre_trig; struct bcm_clk_div pre_div; struct bcm_clk_trig trig;