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[209.132.180.67]) by mx.google.com with ESMTP id bu3si9352040pbb.98.2014.06.20.04.35.32; Fri, 20 Jun 2014 04:35:32 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967131AbaFTLfa (ORCPT + 13 others); Fri, 20 Jun 2014 07:35:30 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:54732 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966619AbaFTLf2 (ORCPT ); Fri, 20 Jun 2014 07:35:28 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s5KBXdnh018839; Fri, 20 Jun 2014 13:34:56 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 1mkws2fk4v-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Fri, 20 Jun 2014 13:34:56 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F20F34E; Fri, 20 Jun 2014 11:34:55 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9875E2CB5F; Fri, 20 Jun 2014 11:34:55 +0000 (GMT) Received: from lmenx29l.st.com ([10.201.23.80]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZN95697 (AUTH lme00137); Fri, 20 Jun 2014 13:34:52 +0200 From: Maxime COQUELIN To: Linus Walleij , Srinivas Kandagatla , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: kernel@stlinux.com, patrice.chotard@st.com, maxime.coquelin@st.com Subject: [PATCH] pinctrl: st: Fix irqmux handler Date: Fri, 20 Jun 2014 13:34:54 +0200 Message-Id: <1403264094-16140-1-git-send-email-maxime.coquelin@st.com> X-Mailer: git-send-email 1.9.1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52, 1.0.14, 0.0.0000 definitions=2014-06-20_04:2014-06-20, 2014-06-20, 1970-01-01 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: maxime.coquelin@st.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , st_gpio_irqmux_handler() reads the status register to find out which banks inside the controller have pending IRQs. For each banks having pending IRQs, it calls the corresponding handler. Problem is that current code restricts the number of possible banks inside the controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins inside a bank, so it shouldn't be used here. On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two last banks (PIO18 & PIO19) aren't handled. This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the controller. Cc: Srinivas Kandagatla Cc: Linus Walleij Cc: #v3.15+ Signed-off-by: Maxime Coquelin Acked-by: Srinivas Kandagatla --- drivers/pinctrl/pinctrl-st.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1bd6363bc9..9f43916 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) status = readl(info->irqmux_base); - for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK) + for_each_set_bit(n, &status, info->nbanks) __gpio_irq_handler(&info->banks[n]); chained_irq_exit(chip, desc);