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[209.132.180.67]) by mx.google.com with ESMTP id of3si14656592pbc.65.2014.07.21.09.02.20; Mon, 21 Jul 2014 09:02:20 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932887AbaGUQCU (ORCPT + 8 others); Mon, 21 Jul 2014 12:02:20 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:48050 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932876AbaGUQCT (ORCPT ); Mon, 21 Jul 2014 12:02:19 -0400 Received: from cpc11-sgyl31-2-0-cust672.sgyl.cable.virginm.net ([94.175.94.161] helo=debutante) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1X9G2O-000276-2B; Mon, 21 Jul 2014 16:02:08 +0000 Received: from broonie by debutante with local (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1X9G2L-0002FT-8V; Mon, 21 Jul 2014 17:02:01 +0100 From: Mark Brown To: Kukjin Kim Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Victor Kamensky , Mark Brown Date: Mon, 21 Jul 2014 17:01:47 +0100 Message-Id: <1405958507-8606-1-git-send-email-broonie@kernel.org> X-Mailer: git-send-email 2.0.1 X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mezzanine.sirena.org.uk X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.2 Subject: [PATCH] exynos: Support big endian mode in secondary_startup X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: broonie@kernel.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Victor Kamensky Exynos processors generally operate in little endian mode so their bootloader and ROM will almost always operate in little endian mode. This means that if a big endian kernel is run it must switch the CPU into big endian mode after gaining control. The generic secondary_startup that is called from exynos specific secondary startup code will do the switch, but we need it to do earlier because exynos specific secondary_startup code which runs first also works with data that is big endian when the kernel is compiled for big endian. [Rewrote commit message. -- broonie] Signed-off-by: Victor Kamensky Signed-off-by: Mark Brown --- arch/arm/mach-exynos/headsmp.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index b54f9701e421..ac8364efb985 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -18,6 +18,11 @@ * ready for them to initialise. */ ENTRY(exynos4_secondary_startup) + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it to big endian mode. + */ +ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 adr r4, 1f