From patchwork Tue Aug 26 14:13:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 36026 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f199.google.com (mail-qc0-f199.google.com [209.85.216.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B90702054F for ; Tue, 26 Aug 2014 14:13:51 +0000 (UTC) Received: by mail-qc0-f199.google.com with SMTP id x3sf46725050qcv.6 for ; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=daApoMC6DTgNWIa2aRjUSSXbwPuCU1tZefbuNBCPJlQ=; b=EKrEKiPmE2z87s41xWeuu65L9jAZrJpXN44MZREMu7zg6wRHsd6SDxZqdspXMLVCVu h4zvPFh7mirUl/1E7X52QDOIHKmkd0P+KPxPl5sjKn8aMl7i6YVRHpfqIbcKoBEN5yfI PbrUioYRP9EZzHNvAA+wP1T7crZZOGr/PkkiL+oFX1576tV2eSkmwSs6DhmshMn6EBW7 Z+bjzYtfuL+HJjPAEOT7OEMb4vaVF3BhUTC+eFyYFvcxu8VNs+KqU0vHvLnrPNyHfHFN xJt/K1UwM+qNfcJgoP5MsqsWte4+HPegKU+yz52IlErjmbl5h323GQeZhstaZvInJymj 4iLA== X-Gm-Message-State: ALoCoQlBW9r3u9z/fBShKt/EtAM3yOMnOKBYB8c4R8rfC/snHJ6ObdQehFidoMKvtS19DCFRS+Cl X-Received: by 10.236.105.197 with SMTP id k45mr5265959yhg.19.1409062431618; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.49.83 with SMTP id p77ls2589373qga.97.gmail; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) X-Received: by 10.236.37.3 with SMTP id x3mr2758883yha.111.1409062431291; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) Received: from mail-yk0-f181.google.com (mail-yk0-f181.google.com [209.85.160.181]) by mx.google.com with ESMTPS id q40si2562573yhg.97.2014.08.26.07.13.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Aug 2014 07:13:51 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.160.181 as permitted sender) client-ip=209.85.160.181; Received: by mail-yk0-f181.google.com with SMTP id q200so11270186ykb.40 for ; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) X-Received: by 10.52.73.202 with SMTP id n10mr421862vdv.86.1409062431188; Tue, 26 Aug 2014 07:13:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp202594vcb; Tue, 26 Aug 2014 07:13:50 -0700 (PDT) X-Received: by 10.69.18.203 with SMTP id go11mr37518488pbd.50.1409062430318; Tue, 26 Aug 2014 07:13:50 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id uz5si4348235pbc.204.2014.08.26.07.13.49 for ; Tue, 26 Aug 2014 07:13:50 -0700 (PDT) Received-SPF: none (google.com: stable-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758299AbaHZONo (ORCPT + 1 other); Tue, 26 Aug 2014 10:13:44 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:37110 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758272AbaHZONn (ORCPT ); Tue, 26 Aug 2014 10:13:43 -0400 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.34]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s7QEDIwo011809; Tue, 26 Aug 2014 15:13:18 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id DAC661AE062F; Tue, 26 Aug 2014 15:13:37 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, Will Deacon , Subject: [PATCH 09/11] arm64: ptrace: fix compat hardware watchpoint reporting Date: Tue, 26 Aug 2014 15:13:28 +0100 Message-Id: <1409062410-25891-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.0.rc1 In-Reply-To: <1409062410-25891-1-git-send-email-will.deacon@arm.com> References: <1409062410-25891-1-git-send-email-will.deacon@arm.com> Sender: stable-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: stable@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.deacon@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.160.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , I'm not sure what I was on when I wrote this, but when iterating over the hardware watchpoint array (hbp_watch_array), our index is off by ARM_MAX_BRP, so we walk off the end of our thread_struct... ... except, a dodgy condition in the loop means that it never executes at all (bp cannot be NULL). This patch fixes the code so that we remove the bp check and use the correct index for accessing the watchpoint structures. Cc: Signed-off-by: Will Deacon --- arch/arm64/include/asm/hw_breakpoint.h | 1 - arch/arm64/kernel/ptrace.c | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h index d064047612b1..52b484b6aa1a 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -79,7 +79,6 @@ static inline void decode_ctrl_reg(u32 reg, */ #define ARM_MAX_BRP 16 #define ARM_MAX_WRP 16 -#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP) /* Virtual debug register bases. */ #define AARCH64_DBG_REG_BVR 0 diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 70526cfda056..2ac998878001 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -87,7 +87,8 @@ static void ptrace_hbptriggered(struct perf_event *bp, break; } } - for (i = ARM_MAX_BRP; i < ARM_MAX_HBP_SLOTS && !bp; ++i) { + + for (i = 0; i < ARM_MAX_WRP; ++i) { if (current->thread.debug.hbp_watch[i] == bp) { info.si_errno = -((i << 1) + 1); break;