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[209.132.180.67]) by mx.google.com with ESMTP id g3si5671248pdi.100.2014.09.02.05.03.25 for ; Tue, 02 Sep 2014 05:03:26 -0700 (PDT) Received-SPF: none (google.com: linux-pm-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753391AbaIBMDT (ORCPT + 14 others); Tue, 2 Sep 2014 08:03:19 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:61538 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753268AbaIBMDS (ORCPT ); Tue, 2 Sep 2014 08:03:18 -0400 Received: by mail-wi0-f173.google.com with SMTP id cc10so7241470wib.6 for ; Tue, 02 Sep 2014 05:03:17 -0700 (PDT) X-Received: by 10.194.119.193 with SMTP id kw1mr15683610wjb.82.1409659397827; Tue, 02 Sep 2014 05:03:17 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id hm5sm9125196wjb.2.2014.09.02.05.03.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Sep 2014 05:03:17 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, linux-pm@vger.kernel.org Cc: Arnd Bergmann , Pawel Moll , Mark Rutland , Marc Zyngier , Will Deacon , Rob Herring , Linus Walleij , Florian Fainelli Subject: [PATCH 7/8] ARM: l2x0: support associativity from DT Date: Tue, 2 Sep 2014 14:02:33 +0200 Message-Id: <1409659354-23553-8-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1409659354-23553-1-git-send-email-linus.walleij@linaro.org> References: <1409659354-23553-1-git-send-email-linus.walleij@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The ARM RealView platforms comes with boot loaders that fail to set up cache size, ways and associativity correctly. This complements Florian's patch to set up cache size and sets from the device tree with the possibility to set up associativity on the L2C-220 cache variant. Cc: Florian Fainelli Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/l2cc.txt | 1 + arch/arm/mm/cache-l2x0.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index d33ed2344c7e..94b02f704f1d 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,7 @@ Optional properties: I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. +- cache-associativity : specifies the associativity of the cache - cache-size : specifies the size in bytes of the cache - cache-sets : specifies the number of associativity sets of the cache - cache-id-part: cache id part number to be used if it is not present diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c735f792c3d5..ebed9638b96c 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1007,6 +1007,7 @@ static void __init l2x0_of_parse(const struct device_node *np, u32 tag = 0; u32 dirty = 0; u32 val = 0, mask = 0; + u32 assoc = 0; of_property_read_u32(np, "arm,tag-latency", &tag); if (tag) { @@ -1029,6 +1030,16 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; } + of_property_read_u32(np, "cache-associativity", &assoc); + if (assoc) { + if (assoc > 8) { + pr_warn("L2C: associativity %d is too large\n", assoc); + } else { + mask |= L2X0_AUX_CTRL_ASSOC_MASK; + val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); + } + } + l2x0_cache_size_of_parse(np, aux_val, aux_mask, SZ_256K); *aux_val &= ~mask;