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Date: Mon, 3 Nov 2014 20:34:03 +0530 Message-Id: <1415027045-6573-4-git-send-email-yogesh.tillu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> References: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141103_070900_540224_42F1B045 X-CRM114-Status: GOOD ( 16.96 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.54 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.54 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: magnus.karlsson@avagotech.com, tillu.yogesh@gmail.com, Prasun.Kapoor@caviumnetworks.com, linux-perf-users@vger.kernel.org, Andrew.Pinski@caviumnetworks.com, mike.holmes@linaro.org, ola.liljedahl@linaro.org, Yogesh Tillu , linaro-networking@linaro.org, jean.pihet@linaro.org, arnd@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: yogesh.tillu@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patchset contains Test application for accessing perf cycle counter from userspace using asm. Signed-off-by: Yogesh Tillu --- README.directaccess | 8 ++++ direct_access.c | 65 ++++++++++++++++++++++++++++ direct_access.h | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) create mode 100644 README.directaccess create mode 100644 direct_access.c create mode 100644 direct_access.h diff --git a/README.directaccess b/README.directaccess new file mode 100644 index 0000000..99e929c --- /dev/null +++ b/README.directaccess @@ -0,0 +1,8 @@ +To Cross-compile application: + ~/arm64-tc-14.06/bin/aarch64-linux-gnu-gcc -std=gnu99 -O3 direct_access.c + -o direct_access + +Run: +1) Insert kernel module to enable userspace access of perf cycle counter +2) $./direct_access 64 [ Pass same random number as with test + of perf_event_open ] diff --git a/direct_access.c b/direct_access.c new file mode 100644 index 0000000..7a9e9b2 --- /dev/null +++ b/direct_access.c @@ -0,0 +1,65 @@ +#include +#include +#include +#include "direct_access.h" +/* Simple loop body to keep things interested. Make sure it gets inlined. */ +static inline int +loop(int* __restrict__ a, int* __restrict__ b, int n) +{ + unsigned sum = 0; + for (int i = 0; i < n; ++i) + if(a[i] > b[i]) + sum += a[i] + 5; + return sum; +} + +int +main(int ac, char **av) +{ + uint32_t time_start = 0; + uint32_t time_end = 0; + int result=0; + int *a = NULL; + int *b = NULL; + int len = 0; + int sum = 0; + int i; + + if (ac != 2) return -1; + len = atoi(av[1]); + + a = malloc(len*sizeof(*a)); + b = malloc(len*sizeof(*b)); + + for (int i = 0; i < len; ++i) { + a[i] = i+128; + b[i] = i+64; + } +/* Open Counter */ + if(odph_perf_open_counter()!=0) + { + printf("Error in perf_open_counter\n"); + goto cleanup; + } + printf("\nbeginning busy loop for %s len=%d \n", av[0],len); +/* Read Counter with Busy loop */ + time_start = odph_perf_read_counter(); + sum = loop(a, b, len); + time_end = odph_perf_read_counter(); + printf("**********************************************************************\n"); + printf("Busyloop sum = %d\nTime delta Including Busyloop = %lu [clockcycle]\n", sum, time_end - time_start); + +/* Read Counter with profiling read_counter */ + time_start = odph_perf_read_counter(); + odph_perf_read_counter(); + time_end = odph_perf_read_counter(); + printf("\nTime delta Without Busyloop = %lu [clockcycle]\n", time_end - time_start); + printf("**********************************************************************\n"); + +/* Close Counter */ + odph_perf_close_counter(); + free(a); free(b); + return 0; +cleanup: + return -1; +} diff --git a/direct_access.h b/direct_access.h new file mode 100644 index 0000000..f7ac20b --- /dev/null +++ b/direct_access.h @@ -0,0 +1,117 @@ +/* Copyright (c) 2014, Linaro Limited + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/** + * @file + * + * Performance Counter Direct access Header + */ + +#ifndef DIRECT_ACCESS_H_ +#define DIRECT_ACCESS_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#if __aarch64__ /**< Check for ArmV8 */ +#define ARMV8_PMCNTENSET_EL0_ENABLE (1<<31) /**< Enable Perf count reg */ +#endif + +/** + * Open Performance counter + * + * @note api to enable performance counters in system, this function does + * enable sequence for respective arm versions + * + * @param void + * + * @return 0 if open successfully, otherwise -1 + */ +static inline int odph_perf_open_counter(void) +{ + +#if __aarch64__ +/* Performance Monitors Count Enable Set register bit 31:0 disable, 1 enable */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (ARMV8_PMCNTENSET_EL0_ENABLE)); + return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported Architecture + return -1; +#endif +} + +/** + * Read Performance counter + * + * @note api to read performance cycle counters in system + * + * @param void + * + * @return cycle counter value if read successfully, otherwise -1 + */ +static inline uint64_t +odph_perf_read_counter(void) +{ +uint64_t ret = 0; +#if defined __aarch64__ + asm volatile("mrs %0, pmccntr_el0" : "=r" (ret)); + return ret; +#elif defined(__ARM_ARCH_7A__) + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(ret)); + return ret; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +/** + * Write Performance counter + * + * @note api to write value to Performance counter, + * NA for now + * + * @param void + * + * @return 0 if written successfully, otherwise -1 + */ +static inline int odph_perf_write_counter(void) +{ +/* Stub */ +} + +/** + * Close Performance counter + * + * @note api to perform close sequnce for cycle counters in system + * + * @param void + * + * @return 0 if close successfully, otherwise -1 + */ +static inline int odph_perf_close_counter(void) +{ +#if defined __aarch64__ + /* Performance Monitors Count Enable Set register bit 31:0 disable, 1 enable */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (0<<31)); + /* Note above statement does not really clearing register...refer to doc */ + return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* DIRECT_ACCESS_H_ */