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[83.153.85.71]) by mx.google.com with ESMTPSA id cz3sm6924303wjb.23.2014.11.26.08.10.06 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 26 Nov 2014 08:10:07 -0800 (PST) From: Ard Biesheuvel To: nico@linaro.org, linux@arm.linux.org.uk, dave.martin@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: add partial interworking support to Thumb-2 kernel Date: Wed, 26 Nov 2014 17:10:09 +0100 Message-Id: <1417018209-14078-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1417018209-14078-1-git-send-email-ard.biesheuvel@linaro.org> References: <1417018209-14078-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141126_081034_034353_BD38C5D5 X-CRM114-Status: GOOD ( 19.70 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.172 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.172 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 ARM/Thumb interworking is currently not allowed in modules at all: external module dependencies can only be fulfilled by symbols of the same flavour, but even inside a module, jumps and calls between objects are rejected if they would incur a mode switch. This patch relaxes that restriction somewhat, by allowing function calls ('bl') from T32 into A32 code. If a non-Thumb function symbol is encountered, a 'bl' instruction is converted into a 'blx' instruction, with the appropriate rounding applied to the offset. The most compelling argument for allowing this is that many modules, especially accelerated crypto, follow the pattern of a core object coded in assembly that is wired up to the kernel APIs using a glue object coded in C. With this patch, such assembly core objects no longer have to be developed, tested and maintained in both ARM and Thumb-2 modes: just having an ARM version suffices. Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/module.c | 40 +++++++++++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 6c08b2188992..ceb1812c2bbc 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -180,8 +180,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: /* - * For function symbols, only Thumb addresses are - * allowed (no interworking). + * For function symbols, we need to force a + * Thumb -> ARM mode switch if the destination + * address has its Thumb bit (bit 0) cleared. * This applies equally to untyped symbols that * resolve to external ksyms: EXPORT_SYMBOL() * strips the function annotation, but we can @@ -197,9 +198,21 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, (ELF32_ST_TYPE(sym->st_info) == STT_NOTYPE && sym->st_shndx == SHN_UNDEF)) && !(sym->st_value & 1)) { - pr_err("%s: section %u reloc %u sym '%s': unsupported interworking call (Thumb -> ARM)\n", - module->name, relindex, i, symname); - return -ENOEXEC; + + /* + * Only interworking call relocations can + * be supported, as long as the destination + * is in range. + */ + if (ELF32_R_TYPE(rel->r_info) != R_ARM_THM_CALL) { + pr_err("%s: section %u reloc %u sym '%s': unsupported interworking call (Thumb -> ARM)\n", + module->name, relindex, i, + symname); + return -ENOEXEC; + } + tmp = sym->st_value; + } else { + tmp = sym->st_value | 1; } upper = __mem_to_opcode_thumb16(*(u16 *)loc); @@ -227,7 +240,17 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, ((lower & 0x07ff) << 1); if (offset & 0x01000000) offset -= 0x02000000; - offset += sym->st_value - loc; + offset += tmp; + + /* + * When fixing up a bl instruction to blx, the address + * of the call site must be rounded down in the + * calculation of 'offset'. As this could potentially + * cause 'offset' to go out of range, we need to do + * this before performing the range check. + */ + tmp = offset & 1 ? loc : loc & ~2; + offset -= tmp; /* * Route through a PLT entry if 'offset' exceeds the @@ -237,8 +260,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, (offset <= (s32)0xff000000 || offset >= (s32)0x01000000)) offset = get_module_plt(module, loc, - offset + loc + 4) + offset + tmp + 4) - loc - 4; + else if (!(offset & 1)) + /* fix up bl -> blx */ + lower &= ~(1 << 12); if (offset <= (s32)0xff000000 || offset >= (s32)0x01000000) {