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[2001:1868:205::9]) by mx.google.com with ESMTPS id yl7si8849362pbc.250.2015.03.05.03.54.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Mar 2015 03:54:28 -0800 (PST) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YTUK9-000355-BD; Thu, 05 Mar 2015 11:52:17 +0000 Received: from mail-wi0-f178.google.com ([209.85.212.178]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YTUK6-0002kP-Rj for linux-arm-kernel@lists.infradead.org; Thu, 05 Mar 2015 11:52:15 +0000 Received: by wibbs8 with SMTP id bs8so6362228wib.4 for ; Thu, 05 Mar 2015 03:51:51 -0800 (PST) X-Received: by 10.180.72.208 with SMTP id f16mr21518188wiv.17.1425556311127; Thu, 05 Mar 2015 03:51:51 -0800 (PST) Received: from ards-macbook-pro.local ([213.143.61.194]) by mx.google.com with ESMTPSA id kr5sm10189886wjc.1.2015.03.05.03.51.48 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 05 Mar 2015 03:51:50 -0800 (PST) From: Ard Biesheuvel To: linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com Subject: [PATCH v2] ARM: advertise availability of v8 Crypto instructions Date: Thu, 5 Mar 2015 12:51:42 +0100 Message-Id: <1425556302-3370-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150305_035215_093222_E33616D0 X-CRM114-Status: GOOD ( 12.28 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.178 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.178 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ard Biesheuvel , will.deacon@arm.com, nico@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 When running the 32-bit ARM kernel on ARMv8 capable bare metal (e.g., 32-bit Android userland and kernel on a Cortex-A53), or as a KVM guest on a 64-bit host, we should advertise the availability of the Crypto instructions, so that userland libraries such as OpenSSL may use them. (Support for the v8 Crypto instructions in the 32-bit build was added to OpenSSL more than six months ago) This adds the ID feature bit detection, and sets elf_hwcap2 accordingly. Signed-off-by: Ard Biesheuvel --- v2: - drop redundant architecture check -> accessing ID_ISAR5 should be safe even on v7-M, and even if we don't expect to find crypto features there - add comment regarding pmull->aes arch/arm/kernel/setup.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index e55408e96559..482bdfa24daa 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -375,7 +375,7 @@ void __init early_print(const char *str, ...) static void __init cpuid_init_hwcaps(void) { - unsigned int divide_instrs, vmsa; + unsigned int divide_instrs, vmsa, isar5; if (cpu_architecture() < CPU_ARCH_ARMv7) return; @@ -393,6 +393,20 @@ static void __init cpuid_init_hwcaps(void) vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0; if (vmsa >= 5) elf_hwcap |= HWCAP_LPAE; + + /* check for supported v8 Crypto instructions */ + isar5 = read_cpuid_ext(CPUID_EXT_ISAR5); + + switch ((isar5 >> 4) & 0xf) { + case 2: elf_hwcap2 |= HWCAP2_PMULL; /* pmull implies aes */ + case 1: elf_hwcap2 |= HWCAP2_AES; + } + if (((isar5 >> 8) & 0xf) == 1) + elf_hwcap2 |= HWCAP2_SHA1; + if (((isar5 >> 12) & 0xf) == 1) + elf_hwcap2 |= HWCAP2_SHA2; + if (((isar5 >> 16) & 0xf) == 1) + elf_hwcap2 |= HWCAP2_CRC32; } static void __init elf_hwcap_fixup(void)