From patchwork Mon Mar 30 20:13:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 46534 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f69.google.com (mail-wg0-f69.google.com [74.125.82.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9D5BC218BE for ; Mon, 30 Mar 2015 20:14:24 +0000 (UTC) Received: by wgtj4 with SMTP id j4sf14088678wgt.0 for ; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=JvLYedKiZjpFkTBIw0R8yCj+bRxxsCf5piYJTCzH7lc=; b=ROdBi6H8xYKb9H1V1Q9GHDeTYeqeRnJUGm8wm42G74VB7c+ClN2b3tUxK66/s8Kacl CgY7kf6ZZwEdvaWVSPWS7cBTJZ3GEMLQdyP4Iq6BIRZKNpeteFE0eCnrAt3cvBLgyh77 ZpU20RUvBfVvEJ91t+FGP4zY2sT77buUAZUgn/lz7Tls4H2xMq63C6+BtuWsoZKupYl1 OlmcNorxVnBQVRZtDoQW/IZGXOpxiwaTiqx7KcLj/ep6d0cJnPCiBTzczMkWHgnDUZa2 Dq1Oyi9VSUlqRHYqi3OFYGwSuM8vk7Z4AxK1fBEqEnsCrwzkr/NK4OV4zvYSzbtVkwfy Q+WQ== X-Gm-Message-State: ALoCoQncIoaynE4RLJZH+eVZ6GRxf3+8UWgUc5cu/vrYxG4GSAjVhR/gNdk91qpaw2HSq4lDgL2f X-Received: by 10.152.8.108 with SMTP id q12mr3520655laa.6.1427746462909; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.36.163 with SMTP id r3ls273634laj.70.gmail; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) X-Received: by 10.112.118.73 with SMTP id kk9mr3290102lbb.3.1427746462697; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) Received: from mail-la0-f46.google.com (mail-la0-f46.google.com. [209.85.215.46]) by mx.google.com with ESMTPS id s4si7715627lag.140.2015.03.30.13.14.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Mar 2015 13:14:22 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) client-ip=209.85.215.46; Received: by lahp7 with SMTP id p7so93835493lah.2 for ; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) X-Received: by 10.152.5.72 with SMTP id q8mr10617881laq.73.1427746462575; Mon, 30 Mar 2015 13:14:22 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.57.201 with SMTP id k9csp1366412lbq; Mon, 30 Mar 2015 13:14:21 -0700 (PDT) X-Received: by 10.66.119.238 with SMTP id kx14mr62090615pab.2.1427746460639; Mon, 30 Mar 2015 13:14:20 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ip9si4685332pbc.136.2015.03.30.13.14.19; Mon, 30 Mar 2015 13:14:20 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754230AbbC3UOG (ORCPT + 27 others); Mon, 30 Mar 2015 16:14:06 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:35964 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753671AbbC3UOB (ORCPT ); Mon, 30 Mar 2015 16:14:01 -0400 Received: by padcy3 with SMTP id cy3so176912393pad.3 for ; Mon, 30 Mar 2015 13:14:01 -0700 (PDT) X-Received: by 10.68.69.103 with SMTP id d7mr17677057pbu.145.1427746441196; Mon, 30 Mar 2015 13:14:01 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id jy9sm11549978pbc.31.2015.03.30.13.14.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Mar 2015 13:14:00 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, kaixu.xia@linaro.org, mathieu.poirier@linaro.org Subject: [PATCH 7/8] coresight-tmc: Adding a status interface to sysfs Date: Mon, 30 Mar 2015 14:13:40 -0600 Message-Id: <1427746421-31360-8-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427746421-31360-1-git-send-email-mathieu.poirier@linaro.org> References: <1427746421-31360-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Knowing the state of various control register is always useful for degging and tuning. As such add an entry in sysfs that expose to userspace the most important registers. Signed-off-by: Mathieu Poirier --- drivers/coresight/coresight-tmc.c | 56 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/coresight/coresight-tmc.c b/drivers/coresight/coresight-tmc.c index 030e097c4fb2..7147f3dd363c 100644 --- a/drivers/coresight/coresight-tmc.c +++ b/drivers/coresight/coresight-tmc.c @@ -565,6 +565,59 @@ static const struct file_operations tmc_fops = { .llseek = no_llseek, }; +static ssize_t status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + unsigned long flags; + u32 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg; + u32 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr; + u32 devid; + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = clk_prepare_enable(drvdata->clk); + if (ret) + goto out; + + spin_lock_irqsave(&drvdata->spinlock, flags); + CS_UNLOCK(drvdata->base); + + tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ); + tmc_sts = readl_relaxed(drvdata->base + TMC_STS); + tmc_rrp = readl_relaxed(drvdata->base + TMC_RRP); + tmc_rwp = readl_relaxed(drvdata->base + TMC_RWP); + tmc_trg = readl_relaxed(drvdata->base + TMC_TRG); + tmc_ctl = readl_relaxed(drvdata->base + TMC_CTL); + tmc_ffsr = readl_relaxed(drvdata->base + TMC_FFSR); + tmc_ffcr = readl_relaxed(drvdata->base + TMC_FFCR); + tmc_mode = readl_relaxed(drvdata->base + TMC_MODE); + tmc_pscr = readl_relaxed(drvdata->base + TMC_PSCR); + devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); + + CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + clk_disable_unprepare(drvdata->clk); + + return sprintf(buf, + "Depth:\t\t0x%x\n" + "Status:\t\t0x%x\n" + "RAM read ptr:\t0x%x\n" + "RAM wrt ptr:\t0x%x\n" + "Trigger cnt:\t0x%x\n" + "Control:\t0x%x\n" + "Flush status:\t0x%x\n" + "Flush ctrl:\t0x%x\n" + "Mode:\t\t0x%x\n" + "PSRC:\t\t0x%x\n" + "DEVID:\t\t0x%x\n", + tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg, + tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr, devid); +out: + return -EINVAL; +} +static DEVICE_ATTR_RO(status); + static ssize_t trigger_cntr_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -593,18 +646,21 @@ static DEVICE_ATTR_RW(trigger_cntr); static struct attribute *coresight_etb_attrs[] = { &dev_attr_trigger_cntr.attr, + &dev_attr_status.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_etb); static struct attribute *coresight_etr_attrs[] = { &dev_attr_trigger_cntr.attr, + &dev_attr_status.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_etr); static struct attribute *coresight_etf_attrs[] = { &dev_attr_trigger_cntr.attr, + &dev_attr_status.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_etf);