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[2001:1868:205::9]) by mx.google.com with ESMTPS id di3si15795493pbc.171.2015.04.17.02.02.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Apr 2015 02:02:49 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yj29B-0006L3-6L; Fri, 17 Apr 2015 09:01:13 +0000 Received: from mail-la0-f46.google.com ([209.85.215.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yj280-0004eI-2f for linux-arm-kernel@lists.infradead.org; Fri, 17 Apr 2015 09:00:01 +0000 Received: by layy10 with SMTP id y10so75188454lay.0 for ; Fri, 17 Apr 2015 01:59:37 -0700 (PDT) X-Received: by 10.152.22.104 with SMTP id c8mr1633283laf.87.1429261177811; Fri, 17 Apr 2015 01:59:37 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id f7sm2271119lam.17.2015.04.17.01.59.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Apr 2015 01:59:36 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Mathieu Poirier Subject: [PATCH 04/13] coresight: tpiu: let runtime PM handle core clock Date: Fri, 17 Apr 2015 10:58:51 +0200 Message-Id: <1429261140-13910-5-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1429261140-13910-1-git-send-email-linus.walleij@linaro.org> References: <1429261140-13910-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150417_020000_339167_A65E7536 X-CRM114-Status: GOOD ( 15.59 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.46 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.46 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ulf Hansson , "Rafael J. Wysocki" , Russell King , Linus Walleij , Trollkarlen Marklund X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will uprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Signed-off-by: Linus Walleij Reviewed-by: Ulf Hansson --- drivers/coresight/coresight-tpiu.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/coresight/coresight-tpiu.c b/drivers/coresight/coresight-tpiu.c index 88b6b0c32538..688ba937069e 100644 --- a/drivers/coresight/coresight-tpiu.c +++ b/drivers/coresight/coresight-tpiu.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include @@ -51,13 +51,11 @@ * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. * @csdev: component vitals needed by the framework. - * @clk: the clock this component is associated to. */ struct tpiu_drvdata { void __iomem *base; struct device *dev; struct coresight_device *csdev; - struct clk *clk; }; static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) @@ -72,12 +70,8 @@ static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) static int tpiu_enable(struct coresight_device *csdev) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int ret; - - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(csdev->dev.parent); tpiu_enable_hw(drvdata); dev_info(drvdata->dev, "TPIU enabled\n"); @@ -101,8 +95,7 @@ static void tpiu_disable(struct coresight_device *csdev) struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); tpiu_disable_hw(drvdata); - - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(csdev->dev.parent); dev_info(drvdata->dev, "TPIU disabled\n"); } @@ -118,7 +111,6 @@ static const struct coresight_ops tpiu_cs_ops = { static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -148,15 +140,10 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) drvdata->base = base; - drvdata->clk = adev->pclk; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; - /* Disable tpiu to support older devices */ tpiu_disable_hw(drvdata); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(&adev->dev); desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); if (!desc)