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[2001:1868:205::9]) by mx.google.com with ESMTPS id nx16si28213242pdb.158.2015.04.20.06.04.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Apr 2015 06:04:32 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YkBKg-0003oz-Gn; Mon, 20 Apr 2015 13:01:50 +0000 Received: from mail-lb0-f179.google.com ([209.85.217.179]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YkBIo-0001sl-Mu for linux-arm-kernel@lists.infradead.org; Mon, 20 Apr 2015 12:59:56 +0000 Received: by lbcga7 with SMTP id ga7so129918876lbc.1 for ; Mon, 20 Apr 2015 05:59:36 -0700 (PDT) X-Received: by 10.152.29.42 with SMTP id g10mr4327118lah.58.1429534776058; Mon, 20 Apr 2015 05:59:36 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id n10sm4295457laa.40.2015.04.20.05.59.34 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Apr 2015 05:59:35 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Mathieu Poirier Subject: [PATCH 08/13 v2] coresight: etm: retrieve and handle atclk Date: Mon, 20 Apr 2015 14:59:01 +0200 Message-Id: <1429534746-3068-8-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1429534746-3068-1-git-send-email-linus.walleij@linaro.org> References: <1429534746-3068-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150420_055955_001066_C9E53CF9 X-CRM114-Status: GOOD ( 18.71 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.217.179 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.217.179 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Ulf Hansson , "Rafael J. Wysocki" , Russell King , Linus Walleij , Trollkarlen Marklund X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 As can be seen from the datasheet of the CoreSight Components, DDI0401C A.1.1 the ETM has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Rebased on the coresight git tree. - Get driver data directly from the device in runtime suspend/resume hooks and skip the intermediate conversion to AMBA device. - Added Ulf's review tag. --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 36 ++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index d1421e1f8b8a..098ffbec0a44 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -140,6 +140,7 @@ * struct etm_drvdata - specifics associated to an ETM component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. + * @atclk: optional clock for the core parts of the ETM. * @csdev: component vitals needed by the framework. * @spinlock: only one at a time pls. * @cpu: the cpu this component is affined to. @@ -191,6 +192,7 @@ struct etm_drvdata { void __iomem *base; struct device *dev; + struct clk *atclk; struct coresight_device *csdev; spinlock_t spinlock; int cpu; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index f0be12bd79e0..4da203cc9c8e 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -1315,7 +1316,6 @@ static ssize_t seq_curr_state_show(struct device *dev, } pm_runtime_get_sync(drvdata->dev); - spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -1796,6 +1796,13 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); + drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + if (!IS_ERR(drvdata->atclk)) { + ret = clk_prepare_enable(drvdata->atclk); + if (ret) + return ret; + } + drvdata->cpu = pdata ? pdata->cpu : 0; get_online_cpus(); @@ -1858,6 +1865,32 @@ static int etm_remove(struct amba_device *adev) return 0; } +#ifdef CONFIG_PM +static int etm_runtime_suspend(struct device *dev) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + + return 0; +} + +static int etm_runtime_resume(struct device *dev) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_prepare_enable(drvdata->atclk); + + return 0; +} +#endif + +static const struct dev_pm_ops etm_dev_pm_ops = { + SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL) +}; + static struct amba_id etm_ids[] = { { /* ETM 3.3 */ .id = 0x0003b921, @@ -1886,6 +1919,7 @@ static struct amba_driver etm_driver = { .drv = { .name = "coresight-etm3x", .owner = THIS_MODULE, + .pm = &etm_dev_pm_ops, }, .probe = etm_probe, .remove = etm_remove,