From patchwork Sun Apr 26 14:31:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 47580 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 46D462121F for ; Sun, 26 Apr 2015 14:39:40 +0000 (UTC) Received: by wghm4 with SMTP id m4sf20460603wgh.2 for ; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=CqIPsFyptyPXZy4397d/ZdAv6J4ZaM877tN9TBVxeY4=; b=kIPmdfGsmmi4WUnk9TnHZQKzuDf4v/FqyFivB2mH4Fo64RHYSg0ANtzYjYH79m/9Ka YYoPfGAzEwISgyjP1siTuxLkUGRO2dV44N3E9efR3EPlZjtb8IiWs1DtTXqzaKuv6q05 aAdLkG1tQRpnui73yszHY3nxvxwV0Z2KZYXrCfR8TKqUy/UsnSmkbIvrOF+0gxWsKvGW Pvn92srGHLH/9gFHDK6pCeNUEuCnwQfbV7ksS77/GVmAYhjltdZUaX73AnyztFSAb5qe tQsjiFJNywWW1OjpPRW1oXPvIJTvtX4vUqoSzyzK+zWEn6Ox3KLiZQDDcuDHfGEU3uW2 M6vg== X-Gm-Message-State: ALoCoQnlapr+VINiCQ717/DOrn2E7OwtEP7TXheSAEnGlqN6jb4xb6ApufNXIj0+lanbPvav8uIx X-Received: by 10.112.53.102 with SMTP id a6mr4742292lbp.16.1430059179539; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.178.225 with SMTP id db1ls602832lac.78.gmail; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) X-Received: by 10.152.36.136 with SMTP id q8mr6290062laj.96.1430059179326; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id os6si11673983lbb.7.2015.04.26.07.39.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Apr 2015 07:39:39 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by labbd9 with SMTP id bd9so63800844lab.2 for ; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) X-Received: by 10.153.8.167 with SMTP id dl7mr6460309lad.86.1430059179202; Sun, 26 Apr 2015 07:39:39 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp815394lbt; Sun, 26 Apr 2015 07:39:38 -0700 (PDT) X-Received: by 10.68.237.97 with SMTP id vb1mr14074303pbc.36.1430059177137; Sun, 26 Apr 2015 07:39:37 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id t1si25951216pds.103.2015.04.26.07.39.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Apr 2015 07:39:37 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YmNga-0004IY-5S; Sun, 26 Apr 2015 14:37:32 +0000 Received: from mail-pd0-f175.google.com ([209.85.192.175]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YmNdo-0001FD-9d for linux-arm-kernel@lists.infradead.org; Sun, 26 Apr 2015 14:34:41 +0000 Received: by pdbnk13 with SMTP id nk13so100497655pdb.0 for ; Sun, 26 Apr 2015 07:34:19 -0700 (PDT) X-Received: by 10.68.87.35 with SMTP id u3mr13999068pbz.127.1430058858992; Sun, 26 Apr 2015 07:34:18 -0700 (PDT) Received: from localhost.localdomain ([104.207.83.1]) by mx.google.com with ESMTPSA id x2sm16622905pdm.40.2015.04.26.07.34.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 26 Apr 2015 07:34:18 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/11] ARM: imx: add clk-pllv1 type support Date: Sun, 26 Apr 2015 22:31:09 +0800 Message-Id: <1430058672-9267-9-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430058672-9267-1-git-send-email-shawn.guo@linaro.org> References: <1430058672-9267-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150426_073440_419244_304A229D X-CRM114-Status: GOOD ( 15.50 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.175 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.2 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.175 listed in wl.mailspike.net] Cc: Frank Li , Stephen Boyd , Russell King , kernel@pengutronix.de, Mike Turquette , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shawn.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1 type support to handle the difference/quirk in particular SoC designs. Doing so will help get clk-pllv1 driver ready for being moved out of arch/arm/mach-imx folder. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx1.c | 4 ++-- arch/arm/mach-imx/clk-imx21.c | 4 ++-- arch/arm/mach-imx/clk-imx25.c | 4 ++-- arch/arm/mach-imx/clk-imx27.c | 4 ++-- arch/arm/mach-imx/clk-imx31.c | 6 +++--- arch/arm/mach-imx/clk-imx35.c | 4 ++-- arch/arm/mach-imx/clk-pllv1.c | 31 ++++++++++++++++++++++++------- arch/arm/mach-imx/clk.h | 13 +++++++++++-- 8 files changed, 48 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 5301d2ebb234..9e68351bb72c 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -50,9 +50,9 @@ static void __init _mx1_clocks_init(unsigned long fref) clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)); - clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); + clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); - clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); + clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index facdf1ddd7f1..bc4254dd40a1 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -63,9 +63,9 @@ static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); - clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); + clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0); - clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0); + clk[IMX21_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "spll", "spll_sel", CCM_SPCTL0); clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 9c2633a9de9f..485d090d2267 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -95,8 +95,8 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, clk[dummy] = imx_clk_fixed("dummy", 0); clk[osc] = imx_clk_fixed("osc", osc_rate); - clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); - clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); + clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); + clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index aeb19982a36e..530af09c6bc7 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -54,8 +54,8 @@ static void __init _mx27_clocks_init(unsigned long fref) clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); - clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); - clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0); + clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); + clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 2aaccadb9e13..caa26ec32152 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -59,9 +59,9 @@ int __init mx31_clocks_init(unsigned long fref) clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckih] = imx_clk_fixed("ckih", fref); clk[ckil] = imx_clk_fixed("ckil", 32768); - clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); - clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL); - clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL); + clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); + clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); + clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 14f33ec049bc..f53d2b502479 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -92,8 +92,8 @@ int __init mx35_clocks_init(void) } clk[ckih] = imx_clk_fixed("ckih", 24000000); - clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); - clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); + clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); + clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index d21d14ca46c1..4e1cb9f39a29 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -26,13 +26,29 @@ struct clk_pllv1 { struct clk_hw hw; void __iomem *base; + enum imx_pllv1_type type; }; #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) -static inline bool mfn_is_negative(unsigned int mfn) +static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) { - return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN); + return pll->type == IMX_PLLV1_IMX1; +} + +static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) +{ + return pll->type == IMX_PLLV1_IMX21; +} + +static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) +{ + return pll->type == IMX_PLLV1_IMX27; +} + +static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) +{ + return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); } static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, @@ -71,8 +87,8 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, * 2's complements number. * On i.MX27 the bit 9 is the sign bit. */ - if (mfn_is_negative(mfn)) { - if (cpu_is_mx27()) + if (mfn_is_negative(pll, mfn)) { + if (is_imx27_pllv1(pll)) mfn_abs = mfn & MFN_MASK; else mfn_abs = BIT(MFN_BITS) - mfn; @@ -85,7 +101,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, do_div(ll, mfd + 1); - if (mfn_is_negative(mfn)) + if (mfn_is_negative(pll, mfn)) ll = -ll; ll = (rate * mfi) + ll; @@ -97,8 +113,8 @@ static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; -struct clk *imx_clk_pllv1(const char *name, const char *parent, - void __iomem *base) +struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, + const char *parent, void __iomem *base) { struct clk_pllv1 *pll; struct clk *clk; @@ -109,6 +125,7 @@ struct clk *imx_clk_pllv1(const char *name, const char *parent, return ERR_PTR(-ENOMEM); pll->base = base; + pll->type = type; init.name = name; init.ops = &clk_pllv1_ops; diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 6a07903a28bc..b5297e457a8e 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -10,8 +10,17 @@ void imx_check_clocks(struct clk *clks[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); -struct clk *imx_clk_pllv1(const char *name, const char *parent, - void __iomem *base); +enum imx_pllv1_type { + IMX_PLLV1_IMX1, + IMX_PLLV1_IMX21, + IMX_PLLV1_IMX25, + IMX_PLLV1_IMX27, + IMX_PLLV1_IMX31, + IMX_PLLV1_IMX35, +}; + +struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, + const char *parent, void __iomem *base); struct clk *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base);