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[209.132.180.67]) by mx.google.com with ESMTP id v1si33041366pbs.72.2015.05.14.09.11.30; Thu, 14 May 2015 09:11:31 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965136AbbENQLV (ORCPT + 7 others); Thu, 14 May 2015 12:11:21 -0400 Received: from mail-la0-f43.google.com ([209.85.215.43]:35493 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965132AbbENQLT (ORCPT ); Thu, 14 May 2015 12:11:19 -0400 Received: by labbd9 with SMTP id bd9so74952636lab.2 for ; Thu, 14 May 2015 09:11:17 -0700 (PDT) X-Received: by 10.152.7.97 with SMTP id i1mr3664871laa.49.1431619877491; Thu, 14 May 2015 09:11:17 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ew6sm6259045lbc.40.2015.05.14.09.11.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 May 2015 09:11:16 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Linus Walleij Subject: [PATCH 1/4] ARM: scu: document Snoop Control Unit DT bindings Date: Thu, 14 May 2015 18:11:04 +0200 Message-Id: <1431619867-14700-2-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1431619867-14700-1-git-send-email-linus.walleij@linaro.org> References: <1431619867-14700-1-git-send-email-linus.walleij@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds device tree bindings for the ARM Cortex-A5 and Cortex-A9 Snoop Control Units. Signed-off-by: Linus Walleij --- Several device trees already contain DT nodes for the Cortex-A9 and Cortex-A5 Snoop Control Units, this documents the already existing and used bindings. --- --- Documentation/devicetree/bindings/arm/scu.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/scu.txt diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt new file mode 100644 index 000000000000..c447680519bb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/scu.txt @@ -0,0 +1,25 @@ +* ARM Snoop Control Unit (SCU) + +As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided +with a Snoop Control Unit. The register range is usually 256 (0x100) +bytes. + +References: + +- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual + Revision r2p0 +- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual + Revision r0p1 + +- compatible : Should be: + "arm,cortex-a9-scu" + "arm,cortex-a5-scu" + +- reg : Specify the base address and the size of the SCU register window. + +Example: + +scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; +};