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[2001:1868:205::9]) by mx.google.com with ESMTPS id do1si26449936pdb.32.2015.07.05.19.19.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Jul 2015 19:19:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBvzX-0005yS-Q6; Mon, 06 Jul 2015 02:18:43 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZBvzO-0005o6-O4 for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2015 02:18:35 +0000 Received: by pacws9 with SMTP id ws9so88337548pac.0 for ; Sun, 05 Jul 2015 19:18:14 -0700 (PDT) X-Received: by 10.68.130.98 with SMTP id od2mr99470796pbb.73.1436149094043; Sun, 05 Jul 2015 19:18:14 -0700 (PDT) Received: from localhost ([120.136.34.248]) by mx.google.com with ESMTPSA id or7sm16230788pdb.9.2015.07.05.19.18.11 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 05 Jul 2015 19:18:12 -0700 (PDT) From: shannon.zhao@linaro.org To: kvmarm@lists.cs.columbia.edu Subject: [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Date: Mon, 6 Jul 2015 10:17:34 +0800 Message-Id: <1436149068-3784-5-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> References: <1436149068-3784-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150705_191834_821679_53A604AF X-CRM114-Status: GOOD ( 13.90 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.51 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.51 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add access handler which emulates writing and reading PMCR_EL0 register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c370b40..152ee17 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -236,6 +237,44 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; } +static void reset_pmcr_el0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u32 pmcr; + + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr)); + vcpu_sys_reg(vcpu, PMCR_EL0) = (pmcr & ~ARMV8_PMCR_MASK) + | (ARMV8_PMCR_MASK & 0xdecafbad); +} + +/* PMCR_EL0 accessor. Only called as long as MDCR_EL2.TPMCR is set. */ +static bool access_pmcr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + unsigned long val; + + if (p->is_write) { + /* Only update writeable bits of PMCR */ + if (!p->is_aarch32) + val = vcpu_sys_reg(vcpu, r->reg); + else + val = vcpu_cp15(vcpu, r->reg); + val &= ~ARMV8_PMCR_MASK; + val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK; + if (!p->is_aarch32) + vcpu_sys_reg(vcpu, r->reg) = val; + else + vcpu_cp15(vcpu, r->reg) = val; + } else { + if (!p->is_aarch32) + *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); + else + *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); + } + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -427,7 +466,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* PMCR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), - trap_raz_wi }, + access_pmcr, reset_pmcr_el0, PMCR_EL0, }, /* PMCNTENSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), trap_raz_wi },