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[2001:1868:205::9]) by mx.google.com with ESMTPS id bk6si24774739pad.202.2015.08.03.00.03.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Aug 2015 00:03:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZM9kk-0003LE-Ot; Mon, 03 Aug 2015 07:01:42 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZM9ke-0003AY-0R for linux-arm-kernel@lists.infradead.org; Mon, 03 Aug 2015 07:01:39 +0000 Received: from 172.24.1.47 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CPR49419; Mon, 03 Aug 2015 15:00:22 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.158.1; Mon, 3 Aug 2015 15:00:13 +0800 From: Shannon Zhao To: , , Subject: [PATCH 1/2] drivers: PL061: add support for platform driver probing Date: Mon, 3 Aug 2015 14:59:57 +0800 Message-ID: <1438585198-8764-2-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1438585198-8764-1-git-send-email-zhaoshenglong@huawei.com> References: <1438585198-8764-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150803_000136_402959_28A9DA42 X-CRM114-Status: GOOD ( 19.03 ) X-Spam-Score: -4.3 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.65 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: shannon.zhao@linaro.org, zhaoshenglong@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Since PL061 currently only supports AMBA driver, to support using GPIO PL061 by DT or ACPI, it needs to add support for platform driver. A DT binding is provided with this patch, ACPI support is added in a separate one. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- drivers/gpio/gpio-pl061.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 0475613..64c10eb 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -24,6 +24,7 @@ #include #include #include +#include #define GPIODIR 0x400 #define GPIOIS 0x404 @@ -241,6 +242,94 @@ static struct irq_chip pl061_irqchip = { .irq_set_type = pl061_irq_type, }; +static int pl061_platform_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pl061_platform_data *pdata = dev_get_platdata(dev); + struct pl061_gpio *chip; + int ret, irq, i, irq_base; + struct resource *mem; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) + return -EINVAL; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + if (pdata) { + chip->gc.base = pdata->gpio_base; + irq_base = pdata->irq_base; + if (irq_base <= 0) { + dev_err(&pdev->dev, "invalid IRQ base in pdata\n"); + return -ENODEV; + } + } else { + chip->gc.base = -1; + irq_base = 0; + } + + chip->base = devm_ioremap(dev, mem->start, resource_size(mem)); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + spin_lock_init(&chip->lock); + if (of_property_read_bool(dev->of_node, "gpio-ranges")) + chip->uses_pinctrl = true; + + chip->gc.request = pl061_gpio_request; + chip->gc.free = pl061_gpio_free; + chip->gc.direction_input = pl061_direction_input; + chip->gc.direction_output = pl061_direction_output; + chip->gc.get = pl061_get_value; + chip->gc.set = pl061_set_value; + chip->gc.ngpio = PL061_GPIO_NR; + chip->gc.label = dev_name(dev); + chip->gc.dev = dev; + chip->gc.owner = THIS_MODULE; + + ret = gpiochip_add(&chip->gc); + if (ret) + return ret; + + /* + * irq_chip support + */ + writeb(0, chip->base + GPIOIE); /* disable irqs */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "invalid IRQ\n"); + return -ENODEV; + } + + ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip, + irq_base, handle_simple_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_info(&pdev->dev, "could not add irqchip\n"); + return ret; + } + gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip, + irq, pl061_irq_handler); + + for (i = 0; i < PL061_GPIO_NR; i++) { + if (pdata) { + if (pdata->directions & (BIT(i))) + pl061_direction_output(&chip->gc, i, + pdata->values & (BIT(i))); + else + pl061_direction_input(&chip->gc, i); + } + } + + platform_set_drvdata(pdev, chip); + dev_info(&pdev->dev, "PL061 GPIO chip @%pa registered\n", + &mem->start); + + return 0; +} + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -376,6 +465,23 @@ static const struct dev_pm_ops pl061_dev_pm_ops = { }; #endif +static const struct of_device_id pl061_of_match[] = { + { .compatible = "arm,pl061", }, + {}, +}; +MODULE_DEVICE_TABLE(of, pl061_of_match); + +static struct platform_driver pl061_gpio_platform_driver = { + .driver = { + .name = "pl061_gpio", + .of_match_table = pl061_of_match, +#ifdef CONFIG_PM + .pm = &pl061_dev_pm_ops, +#endif + }, + .probe = pl061_platform_probe, +}; + static struct amba_id pl061_ids[] = { { .id = 0x00041061, @@ -399,6 +505,8 @@ static struct amba_driver pl061_gpio_driver = { static int __init pl061_gpio_init(void) { + if (platform_driver_register(&pl061_gpio_platform_driver)) + pr_warn("could not register PL061 platform driver\n"); return amba_driver_register(&pl061_gpio_driver); } module_init(pl061_gpio_init);