From patchwork Tue Sep 15 12:49:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Wang X-Patchwork-Id: 53638 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by patches.linaro.org (Postfix) with ESMTPS id 0F3C422A22 for ; Tue, 15 Sep 2015 12:47:24 +0000 (UTC) Received: by wicmn1 with SMTP id mn1sf7792023wic.1 for ; Tue, 15 Sep 2015 05:47:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-type:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe; bh=Gdse6NN3gwhDNnCfXFYZNBywqdvgm3lJUVLafedsSag=; b=JMo1FFaQO4Y0tuFMhI8Fl8NT9WM04IPdB5p0C285Bj/nJMfUK1FuJh6AVHBcgS+xgw tjgBpwywbTb51jbRiXenqA7q3Rkz9N6VPJpxqzupXHe8k2+D8IwX51iyvrXXy+ZqhHgm 2pe+r7c8m79a7ibbpmnhys5Ul6ZgxQfBVPvi5qQd5Yl448/+eQQQtNqByLSUwh4TyR/H dPTr5yLWwlfRYBF6XGe4ttzb31GUiE7UDZ/ZupIHLq/m7VlIXvy6P9xA5Y+hY/5jAo94 3yJDYkWvrH5yFK7NyLDNYvMGFfZA57mM64Q+upajbFVTl8/Dd9iS1pScHhmi98+nALG6 LuUw== X-Gm-Message-State: ALoCoQlkJHSns0J5XhcFzjwM4WMGltLqm1SgrhSnXmuaQPZ8uW1/qpEQw+I5Z8OXfgX3U7yoqS7H X-Received: by 10.112.132.105 with SMTP id ot9mr4228621lbb.21.1442321243300; Tue, 15 Sep 2015 05:47:23 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.4.161 with SMTP id l1ls299047lal.57.gmail; Tue, 15 Sep 2015 05:47:23 -0700 (PDT) X-Received: by 10.152.37.105 with SMTP id x9mr20395707laj.91.1442321243169; Tue, 15 Sep 2015 05:47:23 -0700 (PDT) Received: from mail-lb0-f176.google.com (mail-lb0-f176.google.com. [209.85.217.176]) by mx.google.com with ESMTPS id li9si13351849lbc.121.2015.09.15.05.47.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Sep 2015 05:47:23 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) client-ip=209.85.217.176; Received: by lbbvu2 with SMTP id vu2so12101242lbb.0 for ; Tue, 15 Sep 2015 05:47:23 -0700 (PDT) X-Received: by 10.152.18.130 with SMTP id w2mr11290332lad.88.1442321242931; Tue, 15 Sep 2015 05:47:22 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1782356lbq; Tue, 15 Sep 2015 05:47:21 -0700 (PDT) X-Received: by 10.107.25.71 with SMTP id 68mr31413698ioz.46.1442321241565; Tue, 15 Sep 2015 05:47:21 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n8si11882632igv.46.2015.09.15.05.47.20; Tue, 15 Sep 2015 05:47:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752367AbbIOMrT (ORCPT + 7 others); Tue, 15 Sep 2015 08:47:19 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:48927 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752257AbbIOMrR (ORCPT ); Tue, 15 Sep 2015 08:47:17 -0400 Received: from 172.24.1.49 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.49]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CSJ48641; Tue, 15 Sep 2015 20:43:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Tue, 15 Sep 2015 20:43:23 +0800 From: Zhou Wang To: Bjorn Helgaas , , , Arnd Bergmann , , , , , , , , , , CC: , , , , , , , , , Zhou Wang Subject: [PATCH v9 1/6] PCI: designware: move calculation of bus addresses to DRA7xx Date: Tue, 15 Sep 2015 20:49:16 +0800 Message-ID: <1442321361-174300-2-git-send-email-wangzhou1@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442321361-174300-1-git-send-email-wangzhou1@hisilicon.com> References: <1442321361-174300-1-git-send-email-wangzhou1@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: gabriele paoloni Commit f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated address") added the calculation of PCI BUS addresses in designware, storing them in new fields added in "struct pcie_port". This calculation is done for every designware user even if is only applicable to DRA7xx. This patch moves the calculation of the bus addresses to the DRA7xx driver and is needed to allow the rework of designware to use the new DT parsing API. Signed-off-by: Gabriele Paoloni Signed-off-by: Zhou Wang Acked-by: Pratyush Anand --- drivers/pci/host/pci-dra7xx.c | 13 +++++++++++++ drivers/pci/host/pcie-designware.c | 15 ++++----------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c index 199e29a..ebdffa0 100644 --- a/drivers/pci/host/pci-dra7xx.c +++ b/drivers/pci/host/pci-dra7xx.c @@ -62,6 +62,7 @@ #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C #define LINK_UP BIT(16) +#define CPU_TO_BUS_ADDR 0x0FFFFFFF struct dra7xx_pcie { void __iomem *base; @@ -151,6 +152,18 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) static void dra7xx_pcie_host_init(struct pcie_port *pp) { dw_pcie_setup_rc(pp); + + if (pp->io_mod_base) + pp->io_mod_base &= CPU_TO_BUS_ADDR; + + if (pp->mem_mod_base) + pp->mem_mod_base &= CPU_TO_BUS_ADDR; + + if (pp->cfg0_mod_base) { + pp->cfg0_mod_base &= CPU_TO_BUS_ADDR; + pp->cfg1_mod_base &= CPU_TO_BUS_ADDR; + } + dra7xx_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) dw_pcie_msi_init(pp); diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 52aa6e3..75338a6 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -365,14 +365,10 @@ int dw_pcie_host_init(struct pcie_port *pp) struct of_pci_range range; struct of_pci_range_parser parser; struct resource *cfg_res; - u32 val, na, ns; + u32 val, ns; const __be32 *addrp; int i, index, ret; - /* Find the address cell size and the number of cells in order to get - * the untranslated address. - */ - of_property_read_u32(np, "#address-cells", &na); ns = of_n_size_cells(np); cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); @@ -415,8 +411,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->io_base = range.cpu_addr; /* Find the untranslated IO space address */ - pp->io_mod_base = of_read_number(parser.range - - parser.np + na, ns); + pp->io_mod_base = range.cpu_addr; } if (restype == IORESOURCE_MEM) { of_pci_range_to_resource(&range, np, &pp->mem); @@ -425,8 +420,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->mem_bus_addr = range.pci_addr; /* Find the untranslated MEM space address */ - pp->mem_mod_base = of_read_number(parser.range - - parser.np + na, ns); + pp->mem_mod_base = range.cpu_addr; } if (restype == 0) { of_pci_range_to_resource(&range, np, &pp->cfg); @@ -436,8 +430,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg1_base = pp->cfg.start + pp->cfg0_size; /* Find the untranslated configuration space address */ - pp->cfg0_mod_base = of_read_number(parser.range - - parser.np + na, ns); + pp->cfg0_mod_base = range.cpu_addr; pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; }