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[209.85.215.44]) by mx.google.com with ESMTPS id uk7si9175792lbc.164.2015.10.15.06.47.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:47:17 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by lffy185 with SMTP id y185so27832116lff.2 for ; Thu, 15 Oct 2015 06:47:17 -0700 (PDT) X-Received: by 10.25.82.10 with SMTP id g10mr3099674lfb.56.1444916837611; Thu, 15 Oct 2015 06:47:17 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp644715lbq; Thu, 15 Oct 2015 06:47:16 -0700 (PDT) X-Received: by 10.107.12.140 with SMTP id 12mr7030513iom.33.1444916836456; Thu, 15 Oct 2015 06:47:16 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p10si11691359ioe.7.2015.10.15.06.47.15; Thu, 15 Oct 2015 06:47:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752069AbbJONrP (ORCPT + 7 others); Thu, 15 Oct 2015 09:47:15 -0400 Received: from mail-lf0-f53.google.com ([209.85.215.53]:34932 "EHLO mail-lf0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751007AbbJONrP (ORCPT ); Thu, 15 Oct 2015 09:47:15 -0400 Received: by lffy185 with SMTP id y185so27831014lff.2 for ; Thu, 15 Oct 2015 06:47:13 -0700 (PDT) X-Received: by 10.25.152.211 with SMTP id a202mr3077468lfe.66.1444916833620; Thu, 15 Oct 2015 06:47:13 -0700 (PDT) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id ug9sm2056977lbb.22.2015.10.15.06.47.11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:47:13 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Russell King Cc: Pawel Moll , Mark Rutland , Marc Zyngier , Will Deacon , Rob Herring , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 01/13] ARM: add some L220 DT settings Date: Thu, 15 Oct 2015 15:46:41 +0200 Message-Id: <1444916813-31024-2-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> References: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The RealView ARM11MPCore enables parity, eventmon and shared override in the cache controller through its current boardfile, but the code and DT bindings for the ARM L220 is currently lacking the ability to set this up from DT. Add the required bool parameters. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- I know this patch mixes code and DT changes but it is silly to split such a small patch. Will submit this to Russell's patch tracker if it looks OK to the DT people. (Or if they are quiet.) --- Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++++++---- arch/arm/mm/cache-l2x0.c | 15 +++++++++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 06c88a4d28ac..4d262e9b3464 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -67,12 +67,14 @@ Optional properties: disable if zero. - arm,prefetch-offset : Override prefetch offset value. Valid values are 0-7, 15, 23, and 31. -- arm,shared-override : The default behavior of the pl310 cache controller with - respect to the shareable attribute is to transform "normal memory - non-cacheable transactions" into "cacheable no allocate" (for reads) or - "write through no write allocate" (for writes). +- arm,shared-override : The default behavior of the PL220 or PL310 cache + controllers with respect to the shareable attribute is to transform "normal + memory non-cacheable transactions" into "cacheable no allocate" (for reads) + or "write through no write allocate" (for writes). On systems where this may cause DMA buffer corruption, this property must be specified to indicate that such transforms are precluded. +- arm,parity-enable : enable parity checking on the L2 cache (PL220 only). +- arm,eventmon-enable : enable the event monitor on the L2 cache (PL220 only). - prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> (forcibly enable), property absent (retain settings set by firmware) - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 493692d838c6..d4e9fa2594f3 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1060,6 +1060,21 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; } + if (of_property_read_bool(np, "arm,parity-enable")) { + mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; + val |= L2C_AUX_CTRL_PARITY_ENABLE; + } + + if (of_property_read_bool(np, "arm,eventmon-enable")) { + mask &= ~L2C_AUX_CTRL_EVTMON_ENABLE; + val |= L2C_AUX_CTRL_EVTMON_ENABLE; + } + + if (of_property_read_bool(np, "arm,shared-override")) { + mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; + val |= L2C_AUX_CTRL_SHARED_OVERRIDE; + } + ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); if (ret) return;