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[2001:1868:205::9]) by mx.google.com with ESMTPS id 78si26968208pfm.203.2015.11.29.18.21.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Nov 2015 18:21:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a3E4S-0007gE-Vw; Mon, 30 Nov 2015 02:20:05 +0000 Received: from mail-pa0-x231.google.com ([2607:f8b0:400e:c03::231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a3E1f-0005Zt-BZ for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2015 02:17:12 +0000 Received: by pabfh17 with SMTP id fh17so173107671pab.0 for ; Sun, 29 Nov 2015 18:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gt6BoyEoUq8CInOziVLsFalqiqZKeH8PrkLKEdqNSXw=; b=Sh16yTTQRB97NEsimlQMS3vG12QbXXIypTbdHkkK+Zyv1bxwMQns8JlWCCxIs/eEuW 71bu3nhYf6zBvqCjWXXbYXGPq12ugJf9iTGjxz1J2hd9F+75Mmlm1Cl5XGpkSMX+7Mnl ok3TJObXteyBfilUy7r7jr63AYtZLIco7oz7EqgTxlbyLAG72uF7VaPq39ivnNsuwKBM mWDw90NA3sNSU298DeZ9u8FUjyxQxcoFLa/7aEeQP/otFrowMzeCalrzJkAxCLGv4Opo nb2YVRKdyggbrE2IxrE2KtzmNikZE5t/fAtZ1WBPrq0Pif/ryChfclirf06Ky8+vKxAS RuaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gt6BoyEoUq8CInOziVLsFalqiqZKeH8PrkLKEdqNSXw=; b=jSCXiIkCvhfnMVFWq16rBdy3HFUq4W1f/VVUzHiShoJQtKHdAIJGLbqx69flal3/J5 9GpN9j+pi94dfacT52HpLWOBK51k+ycon+VYaMkFhy4nt6d2bSmUUxon6MKIMHeUKY/f 0qlowwiEKPzwdB8jCsO5rnkFher2czOfmh+0cVcY/U0M5iJJ1kFITN3SCyfoet4Me8o0 n/MPrygp1laJUZFIAZHxOu+miIojAJlzHM5/BXD/pxyyzX2EYZlWk+YK+pfxJVeEucb6 ONKGywjxbsG3unos0m2s/ygVQQhtGyt0nvuVhpkB9GMRjSksIkKN1uPDmQKk5+s8VnIK zZKg== X-Gm-Message-State: ALoCoQnXkIr9gE7EtDPxhmhZSH7KJKKFqSsKbAwaQ2YFgJt54s2IF9mTUvNqLEoX9ku1ZJdgJ/lj X-Received: by 10.67.5.98 with SMTP id cl2mr1353765pad.157.1448849810427; Sun, 29 Nov 2015 18:16:50 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id n16sm47168818pfa.53.2015.11.29.18.16.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Nov 2015 18:16:49 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org, alexander.shishkin@linux.intel.com Subject: [PATCH V5 11/26] coresight: etm3x: changing default trace configuration Date: Sun, 29 Nov 2015 19:14:32 -0700 Message-Id: <1448849687-5724-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1448849687-5724-1-git-send-email-mathieu.poirier@linaro.org> References: <1448849687-5724-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151129_181711_574803_8C0EE0C6 X-CRM114-Status: GOOD ( 15.00 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c03:0:0:0:231 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Mathieu Poirier , pawel.moll@arm.com, linux-doc@vger.kernel.org, fainelli@broadcom.com, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++--------------- 2 files changed, 15 insertions(+), 16 deletions(-) -- 2.1.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index a8663780a908..f01862fc98dd 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -146,6 +146,7 @@ * @startstop_ctrl: setting for register ETMTSSCR. * @enable_event: setting for register ETMTEEVR. * @enable_ctrl1: setting for register ETMTECR1. + * @enable_ctrl2: setting for register ETMTECR2. * @fifofull_level: setting for register ETMFFLR. * @addr_idx: index for the address comparator selection. * @addr_val: value for address comparator register. @@ -179,6 +180,7 @@ struct etm_config { u32 startstop_ctrl; u32 enable_event; u32 enable_ctrl1; + u32 enable_ctrl2; u32 fifofull_level; u8 addr_idx; u32 addr_val[ETM_MAX_ADDR_CMP]; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index a0252ffb4ba7..cfaf8e840bd6 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -608,26 +608,23 @@ static void etm_init_arch_data(void *info) static void etm_init_default_data(struct etm_config *config) { - u32 flags = (1 << 0 | /* instruction execute*/ - 3 << 3 | /* ARM instruction */ - 0 << 5 | /* No data value comparison */ - 0 << 7 | /* No exact mach */ - 0 << 8 | /* Ignore context ID */ - 0 << 10); /* Security ignored */ - if (WARN_ON_ONCE(!config)) return; - config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN); - config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; - config->addr_val[0] = (u32) _stext; - config->addr_val[1] = (u32) _etext; - config->addr_acctype[0] = flags; - config->addr_acctype[1] = flags; - config->addr_type[0] = ETM_ADDR_TYPE_RANGE; - config->addr_type[1] = ETM_ADDR_TYPE_RANGE; - etm_set_default(config); + + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; } static void etm_init_trace_id(struct etm_drvdata *drvdata)