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[2001:1868:205::9]) by mx.google.com with ESMTPS id r14si9838332pfa.184.2015.12.02.22.19.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Dec 2015 22:19:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NDA-0003lC-QR; Thu, 03 Dec 2015 06:17:48 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4N9e-00082j-U1 for linux-arm-kernel@bombadil.infradead.org; Thu, 03 Dec 2015 06:14:11 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1a4N9b-0003uN-Ul for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2015 06:14:10 +0000 Received: from 172.24.1.49 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.49]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAC88351; Thu, 03 Dec 2015 14:12:34 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 3 Dec 2015 14:12:22 +0800 From: Shannon Zhao To: , , Subject: [PATCH v5 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Date: Thu, 3 Dec 2015 14:11:19 +0800 Message-ID: <1449123091-20252-10-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> References: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.565FDD54.0064, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 80e08421c12321635773ded4529dd3b6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151203_011409_303095_8FE317A5 X-CRM114-Status: GOOD ( 11.73 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 53 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6967a49..43a634c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -493,6 +493,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case PMXEVCNTR_EL0: { + u64 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, PMCR_EL0), + idx)) + break; + + val = kvm_pmu_get_counter_value(vcpu, idx); + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + idx) += (s64)*vcpu_reg(vcpu, p->Rt) - val; + break; + } case PMXEVTYPER_EL0: { u64 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK; @@ -524,6 +536,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, } } else { switch (r->reg) { + case PMXEVCNTR_EL0: { + u64 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, PMCR_EL0), + idx)) + break; + + val = kvm_pmu_get_counter_value(vcpu, idx); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } case PMCR_EL0: { /* PMCR.P & PMCR.C are RAZ */ val = vcpu_sys_reg(vcpu, r->reg) @@ -754,7 +778,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), trap_raz_wi }, @@ -967,6 +991,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case c9_PMXEVCNTR: { + u32 idx = vcpu_cp15(vcpu, c9_PMSELR) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, c9_PMCR), + idx)) + break; + + val = kvm_pmu_get_counter_value(vcpu, idx); + vcpu_cp15(vcpu, c14_PMEVCNTR0 + idx) += (s64)*vcpu_reg(vcpu, p->Rt) - val; + break; + } case c9_PMXEVTYPER: { u32 idx = vcpu_cp15(vcpu, c9_PMSELR) & ARMV8_COUNTER_MASK; @@ -998,6 +1034,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, } } else { switch (r->reg) { + case c9_PMXEVCNTR: { + u32 idx = vcpu_cp15(vcpu, c9_PMSELR) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, c9_PMCR), + idx)) + break; + + val = kvm_pmu_get_counter_value(vcpu, idx); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } case c9_PMCR: { /* PMCR.P & PMCR.C are RAZ */ val = vcpu_cp15(vcpu, r->reg) @@ -1056,7 +1104,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, NULL, c9_PMXEVTYPER }, - { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, + NULL, c9_PMXEVCNTR }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },