From patchwork Tue Dec 8 12:47:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57855 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp8002lbb; Tue, 8 Dec 2015 04:55:50 -0800 (PST) X-Received: by 10.66.216.7 with SMTP id om7mr4603202pac.90.1449579350053; Tue, 08 Dec 2015 04:55:50 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id g87si5163385pfj.194.2015.12.08.04.55.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 04:55:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6Hma-0004I5-R6; Tue, 08 Dec 2015 12:54:16 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6Hie-00006C-8O for linux-arm-kernel@bombadil.infradead.org; Tue, 08 Dec 2015 12:50:12 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1a6Hib-0000qD-W7 for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 12:50:11 +0000 Received: from 172.24.1.50 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.50]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAM76591; Tue, 08 Dec 2015 20:48:28 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Dec 2015 20:48:16 +0800 From: Shannon Zhao To: , , Subject: [PATCH v6 14/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Date: Tue, 8 Dec 2015 20:47:33 +0800 Message-ID: <1449578860-15808-15-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> References: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5666D19D.0064, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 095e1312f70ba700dea31f5b51837bf9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_075010_923628_2BF11D7B X-CRM114-Status: GOOD ( 16.17 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, pend PMU interrupt. When the value writing to PMOVSCLR is equal to the current value, clear the PMU pending interrupt. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 27 ++++++++++++++++-- include/kvm/arm_pmu.h | 4 +++ virt/kvm/arm/pmu.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 3 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1dffb2..c830fde 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -601,6 +601,15 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, r->reg) &= ~p->regval; break; } + case PMOVSSET_EL0: { + if (r->CRm == 14) + /* accessing PMOVSSET_EL0 */ + kvm_pmu_overflow_set(vcpu, p->regval); + else + /* accessing PMOVSCLR_EL0 */ + kvm_pmu_overflow_clear(vcpu, p->regval); + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -847,7 +856,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMCNTENSET_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMOVSSET_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), trap_raz_wi }, @@ -874,7 +883,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { trap_raz_wi }, /* PMOVSSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMOVSSET_EL0 }, /* TPIDR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010), @@ -1184,6 +1193,15 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, r->reg) &= ~p->regval; break; } + case c9_PMOVSSET: { + if (r->CRm == 14) + /* accessing c9_PMOVSSET */ + kvm_pmu_overflow_set(vcpu, p->regval); + else + /* accessing c9_PMOVSCLR */ + kvm_pmu_overflow_clear(vcpu, p->regval); + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1271,7 +1289,8 @@ static const struct sys_reg_desc cp15_regs[] = { NULL, c9_PMCNTENSET }, { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs, NULL, c9_PMCNTENSET }, - { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs, + NULL, c9_PMOVSSET }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, NULL, c9_PMSELR }, { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, @@ -1287,6 +1306,8 @@ static const struct sys_reg_desc cp15_regs[] = { NULL, c9_PMINTENSET }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs, NULL, c9_PMINTENSET }, + { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmu_cp15_regs, + NULL, c9_PMOVSSET }, { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index e731656..a76df52 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -41,6 +41,8 @@ struct kvm_pmu { u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val); +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); #else @@ -50,6 +52,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) } void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {} +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {} +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 45586d2..ba7d11c 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -136,6 +136,78 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) } } +static u32 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) +{ + u32 val; + + if (!vcpu_mode_is_32bit(vcpu)) + val = (vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT) + & ARMV8_PMCR_N_MASK; + else + val = (vcpu_cp15(vcpu, c9_PMCR) >> ARMV8_PMCR_N_SHIFT) + & ARMV8_PMCR_N_MASK; + + return GENMASK(val - 1, 0) | BIT(ARMV8_COUNTER_MASK); +} + +/** + * kvm_pmu_overflow_clear - clear PMU overflow interrupt + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMOVSCLR register + * @reg: the current value of PMOVSCLR register + */ +void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) +{ + u32 mask = kvm_pmu_valid_counter_mask(vcpu); + + if (!vcpu_mode_is_32bit(vcpu)) { + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~val; + val = vcpu_sys_reg(vcpu, PMOVSSET_EL0); + } else { + vcpu_cp15(vcpu, c9_PMOVSSET) &= mask; + vcpu_cp15(vcpu, c9_PMOVSSET) &= ~val; + val = vcpu_cp15(vcpu, c9_PMOVSSET); + } + + /* If all overflow bits are cleared, kick the vcpu to clear interrupt + * pending status. + */ + if (val == 0) + kvm_vcpu_kick(vcpu); +} + +/** + * kvm_pmu_overflow_set - set PMU overflow interrupt + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMOVSSET register + */ +void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) +{ + u32 mask = kvm_pmu_valid_counter_mask(vcpu); + + val &= mask; + if (val == 0) + return; + + if (!vcpu_mode_is_32bit(vcpu)) { + vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask; + vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= val; + val = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) + & vcpu_sys_reg(vcpu, PMINTENSET_EL1) + & vcpu_sys_reg(vcpu, PMOVSSET_EL0); + } else { + vcpu_cp15(vcpu, c9_PMOVSSET) &= mask; + vcpu_cp15(vcpu, c9_PMOVSSET) |= val; + val = vcpu_cp15(vcpu, c9_PMCNTENSET) + & vcpu_cp15(vcpu, c9_PMINTENSET) + & vcpu_cp15(vcpu, c9_PMOVSSET); + } + + if (val != 0) + kvm_vcpu_kick(vcpu); +} + /** * kvm_pmu_set_counter_event_type - set selected counter to monitor some event * @vcpu: The vcpu pointer