From patchwork Tue Dec 8 12:47:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57856 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp8298lbb; Tue, 8 Dec 2015 04:56:29 -0800 (PST) X-Received: by 10.98.18.22 with SMTP id a22mr4604239pfj.54.1449579389807; Tue, 08 Dec 2015 04:56:29 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id i13si5150162pat.171.2015.12.08.04.56.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 04:56:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6HnE-0004ry-1W; Tue, 08 Dec 2015 12:54:56 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6HiZ-0007JK-6p for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 12:50:15 +0000 Received: from 172.24.1.50 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.50]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAM76589; Tue, 08 Dec 2015 20:48:27 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Dec 2015 20:48:20 +0800 From: Shannon Zhao To: , , Subject: [PATCH v6 18/21] KVM: ARM64: Add PMU overflow interrupt routing Date: Tue, 8 Dec 2015 20:47:37 +0800 Message-ID: <1449578860-15808-19-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> References: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5666D19C.0120, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 684573df254db5c23ff95462ea3ec84b X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_045008_810995_B0FF805B X-CRM114-Status: GOOD ( 14.71 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c | 2 ++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 1 deletion(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index e06fd29..cd696ef 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -28,6 +28,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" @@ -569,6 +570,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) * non-preemptible context. */ preempt_disable(); + kvm_pmu_flush_hwstate(vcpu); kvm_timer_flush_hwstate(vcpu); kvm_vgic_flush_hwstate(vcpu); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index a131f76..c4041008 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -38,6 +38,7 @@ struct kvm_pmu { }; #ifdef CONFIG_KVM_ARM_PMU +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu); u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); @@ -48,6 +49,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val); #else +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {} u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) { return 0; diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 9b9c706..ff182d6 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -21,6 +21,7 @@ #include #include #include +#include /** * kvm_pmu_get_counter_value - get PMU counter value @@ -90,6 +91,54 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc) } /** + * kvm_pmu_flush_hwstate - flush pmu state to cpu + * @vcpu: The vcpu pointer + * + * Inject virtual PMU IRQ if IRQ is pending for this cpu. + */ +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + u32 overflow; + + if (pmu->irq_num == -1) + return; + + if (!vcpu_mode_is_32bit(vcpu)) { + if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E)) + return; + + overflow = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) + & vcpu_sys_reg(vcpu, PMINTENSET_EL1) + & vcpu_sys_reg(vcpu, PMOVSSET_EL0); + } else { + if (!(vcpu_cp15(vcpu, c9_PMCR) & ARMV8_PMCR_E)) + return; + + overflow = vcpu_cp15(vcpu, c9_PMCNTENSET) + & vcpu_cp15(vcpu, c9_PMINTENSET) + & vcpu_cp15(vcpu, c9_PMOVSSET); + } + + kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num, + overflow ? 1 : 0); +} + +/** + * When perf event overflows, call kvm_pmu_overflow_set to set overflow status. + */ +static void kvm_pmu_perf_overflow(struct perf_event *perf_event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct kvm_pmc *pmc = perf_event->overflow_handler_context; + struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc); + int idx = pmc->idx; + + kvm_pmu_overflow_set(vcpu, BIT(idx)); +} + +/** * kvm_pmu_enable_counter - enable selected PMU counter * @vcpu: The vcpu pointer * @val: the value guest writes to PMCNTENSET register @@ -341,7 +390,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, /* The initial sample period (overflow count) of an event. */ attr.sample_period = (-counter) & pmc->bitmask; - event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); + event = perf_event_create_kernel_counter(&attr, -1, current, + kvm_pmu_perf_overflow, pmc); if (IS_ERR(event)) { printk_once("kvm: pmu event creation failed %ld\n", PTR_ERR(event));