From patchwork Tue Dec 8 12:47:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57853 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp7422lbb; Tue, 8 Dec 2015 04:54:46 -0800 (PST) X-Received: by 10.66.234.8 with SMTP id ua8mr4602603pac.45.1449579286341; Tue, 08 Dec 2015 04:54:46 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id r14si5154009pfa.184.2015.12.08.04.54.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 04:54:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6Hlb-0003JV-5s; Tue, 08 Dec 2015 12:53:15 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6HiS-00070N-KX for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 12:50:09 +0000 Received: from 172.24.1.50 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.50]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAM76564; Tue, 08 Dec 2015 20:48:14 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Dec 2015 20:48:05 +0800 From: Shannon Zhao To: , , Subject: [PATCH v6 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Date: Tue, 8 Dec 2015 20:47:23 +0800 Message-ID: <1449578860-15808-5-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> References: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.5666D18F.0143, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c3212717d720554f78e7d3b70487edad X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_045002_245505_53B11A6D X-CRM114-Status: GOOD ( 13.98 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E to zero. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 2 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d2650e8..beb42f1 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -438,6 +439,58 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; } +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u64 pmcr, val; + + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr)); + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN + * except PMCR.E resetting to zero. + */ + val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad)) + & (~ARMV8_PMCR_E); + vcpu_sys_reg(vcpu, r->reg) = val; +} + +/* PMU registers accessor. */ +static bool access_pmu_regs(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + u64 val; + + if (p->is_write) { + switch (r->reg) { + case PMCR_EL0: { + /* Only update writeable bits of PMCR */ + val = vcpu_sys_reg(vcpu, r->reg); + val &= ~ARMV8_PMCR_MASK; + val |= p->regval & ARMV8_PMCR_MASK; + vcpu_sys_reg(vcpu, r->reg) = val; + break; + } + default: + vcpu_sys_reg(vcpu, r->reg) = p->regval; + break; + } + } else { + switch (r->reg) { + case PMCR_EL0: { + /* PMCR.P & PMCR.C are RAZ */ + val = vcpu_sys_reg(vcpu, r->reg) + & ~(ARMV8_PMCR_P | ARMV8_PMCR_C); + p->regval = val; + break; + } + default: + p->regval = vcpu_sys_reg(vcpu, r->reg); + break; + } + } + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \ @@ -622,7 +675,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* PMCR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), - trap_raz_wi }, + access_pmu_regs, reset_pmcr, PMCR_EL0, }, /* PMCNTENSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), trap_raz_wi }, @@ -856,6 +909,45 @@ static const struct sys_reg_desc cp14_64_regs[] = { { Op1( 0), CRm( 2), .access = trap_raz_wi }, }; +/* PMU CP15 registers accessor. */ +static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + u32 val; + + if (p->is_write) { + switch (r->reg) { + case c9_PMCR: { + /* Only update writeable bits of PMCR */ + val = vcpu_cp15(vcpu, r->reg); + val &= ~ARMV8_PMCR_MASK; + val |= p->regval & ARMV8_PMCR_MASK; + vcpu_cp15(vcpu, r->reg) = val; + break; + } + default: + vcpu_cp15(vcpu, r->reg) = p->regval; + break; + } + } else { + switch (r->reg) { + case c9_PMCR: { + /* PMCR.P & PMCR.C are RAZ */ + val = vcpu_cp15(vcpu, r->reg) + & ~(ARMV8_PMCR_P | ARMV8_PMCR_C); + p->regval = val; + break; + } + default: + p->regval = vcpu_cp15(vcpu, r->reg); + break; + } + } + + return true; +} + /* * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, * depending on the way they are accessed (as a 32bit or a 64bit @@ -884,7 +976,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, /* PMU */ - { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs, + NULL, c9_PMCR }, { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },