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[2001:1868:205::9]) by mx.google.com with ESMTPS id ph6si5136674pac.148.2015.12.08.04.52.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 04:52:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6Hj9-0001KB-JW; Tue, 08 Dec 2015 12:50:43 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6HiF-0006zQ-Os for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 12:49:54 +0000 Received: from 172.24.1.48 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAM76570; Tue, 08 Dec 2015 20:48:17 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Dec 2015 20:48:07 +0800 From: Shannon Zhao To: , , Subject: [PATCH v6 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Date: Tue, 8 Dec 2015 20:47:25 +0800 Message-ID: <1449578860-15808-7-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> References: <1449578860-15808-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.5666D191.02D8, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bdbba4b273bbbb3ddffe6e5f35dd87b4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_044949_310840_564B6CA7 X-CRM114-Status: GOOD ( 11.22 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d81f7ac..1bcb2b7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -452,6 +452,19 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) vcpu_sys_reg(vcpu, r->reg) = val; } +static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u64 pmceid; + + if (r->reg == PMCEID0_EL0) + asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid)); + else + /* PMCEID1_EL0 */ + asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid)); + + vcpu_sys_reg(vcpu, r->reg) = pmceid; +} + /* PMU registers accessor. */ static bool access_pmu_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, @@ -469,6 +482,9 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, r->reg) = val; break; } + case PMCEID0_EL0: + case PMCEID1_EL0: + return ignore_write(vcpu, p); default: vcpu_sys_reg(vcpu, r->reg) = p->regval; break; @@ -693,10 +709,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMSELR_EL0 }, /* PMCEID0_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110), - trap_raz_wi }, + access_pmu_regs, reset_pmceid, PMCEID0_EL0 }, /* PMCEID1_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111), - trap_raz_wi }, + access_pmu_regs, reset_pmceid, PMCEID1_EL0 }, /* PMCCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), trap_raz_wi }, @@ -926,6 +942,9 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, r->reg) = val; break; } + case c9_PMCEID0: + case c9_PMCEID1: + return ignore_write(vcpu, p); default: vcpu_cp15(vcpu, r->reg) = p->regval; break; @@ -983,8 +1002,10 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, NULL, c9_PMSELR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, + NULL, c9_PMCEID0 }, + { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs, + NULL, c9_PMCEID1 }, { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },