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[2001:1868:205::9]) by mx.google.com with ESMTPS id po3si11621260pac.148.2016.01.14.13.50.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jan 2016 13:50:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aJplu-0005yQ-U8; Thu, 14 Jan 2016 21:49:34 +0000 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aJpjw-0004M2-LT for linux-arm-kernel@lists.infradead.org; Thu, 14 Jan 2016 21:47:35 +0000 Received: by mail-pf0-x231.google.com with SMTP id n128so106057697pfn.3 for ; Thu, 14 Jan 2016 13:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8kl1H13Qf43lXukmsZ2x9JTOqelzllCq7748bnS3oTY=; b=R8cr3bP+y8ffRKSNzyiDIw1Dfdvwxx37skn2bxHccCNE55y1fAJbCWc0Ek3fsy/u97 rhP6/LPg7oMYwRoh86R5TIgyauzn+6iIXkqMx3ddJ0cO14W8A4YwqtUHolQ3hPfPJq3q AkIB0pIUh9TdS6FRaHbla2E1TWiWsBNN105S4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8kl1H13Qf43lXukmsZ2x9JTOqelzllCq7748bnS3oTY=; b=KuUpR7q7Q01sTnx8OyLkD1m440LLSYsadABBhjn153R9vQGU2w+ix3fIwELH0nmo/I Ae542qMoCmKUIu20go3t0rI5+MSRH+iqJRT/rirj12OfaQZqf2IYNVmFfIB0z8cbG20D MKwNP+G8xPpowC6uIefZl0rvHUPcFfuEYR1cEiEJcUbatMAAchzK6PuP9KDtO7yX+YE+ ZXpXJdW0fxxd6GgnmL/Aux4F60G9Vm9Wpj++f6OIYOuHy0POousGbOgGl5/wvTf6tOx4 hC7omBEjm3LPTAYyRSuo3j5os+7dmOD9+JCNwJko+g5SGqDCySS+ZNsZTXC+PCHMkfrL hdeA== X-Gm-Message-State: ALoCoQlwZrdLYjdMB9dnDolsBfDf12FeikJTlmcuXED7aeZZn9TwiL0m8bhQ5+gzqedxOuwMc34fdnxsFeKheGJ3JjBj8BHdEw== X-Received: by 10.98.17.79 with SMTP id z76mr9684326pfi.16.1452808036838; Thu, 14 Jan 2016 13:47:16 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id c87sm11383309pfj.41.2016.01.14.13.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jan 2016 13:47:16 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 10/23] coresight: etm3x: changing default trace configuration Date: Thu, 14 Jan 2016 14:46:04 -0700 Message-Id: <1452807977-8069-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> References: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160114_134732_964045_1A9925B3 X-CRM114-Status: GOOD ( 14.22 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:231 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Mathieu Poirier , linux-doc@vger.kernel.org, zhang.chunyan@linaro.org, rabin@rab.in, mike.leach@arm.com, tor@ti.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++--------------- 2 files changed, 15 insertions(+), 16 deletions(-) -- 2.1.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 5b29d5540fe5..44585d4adb26 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -146,6 +146,7 @@ * @startstop_ctrl: setting for register ETMTSSCR. * @enable_event: setting for register ETMTEEVR. * @enable_ctrl1: setting for register ETMTECR1. + * @enable_ctrl2: setting for register ETMTECR2. * @fifofull_level: setting for register ETMFFLR. * @addr_idx: index for the address comparator selection. * @addr_val: value for address comparator register. @@ -179,6 +180,7 @@ struct etm_config { u32 startstop_ctrl; u32 enable_event; u32 enable_ctrl1; + u32 enable_ctrl2; u32 fifofull_level; u8 addr_idx; u32 addr_val[ETM_MAX_ADDR_CMP]; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 82d1557f4ecf..6469d7a83aa1 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -579,26 +579,23 @@ static void etm_init_arch_data(void *info) static void etm_init_default_data(struct etm_config *config) { - u32 flags = (1 << 0 | /* instruction execute*/ - 3 << 3 | /* ARM instruction */ - 0 << 5 | /* No data value comparison */ - 0 << 7 | /* No exact mach */ - 0 << 8 | /* Ignore context ID */ - 0 << 10); /* Security ignored */ - if (WARN_ON_ONCE(!config)) return; - config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN); - config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; - config->addr_val[0] = (u32) _stext; - config->addr_val[1] = (u32) _etext; - config->addr_acctype[0] = flags; - config->addr_acctype[1] = flags; - config->addr_type[0] = ETM_ADDR_TYPE_RANGE; - config->addr_type[1] = ETM_ADDR_TYPE_RANGE; - etm_set_default(config); + + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; } static void etm_init_trace_id(struct etm_drvdata *drvdata)