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[2001:1868:205::9]) by mx.google.com with ESMTPS id x1si25102387pfb.185.2016.04.21.01.06.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 01:06:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@jms.id.au; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9cJ-000554-PR; Thu, 21 Apr 2016 08:05:39 +0000 Received: from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9br-0003aC-9u for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:05:12 +0000 Received: by mail-pf0-x234.google.com with SMTP id n1so27722547pfn.2 for ; Thu, 21 Apr 2016 01:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=AK8VJuru84i5wdeMhe5WEpTdJOdUxMHOxZOH3ilxABw=; b=Pm0R0zm3iUuCvDA9eUe5EJKT3gxKZslTe3xNGASZPggMVYI5IH8/FPsDpEJTkz3DZU GbWh/gkC2Tc18rwJ1KlaiSx6tQDDspIQ9RIstBKNhNZ+eyvsYHYEPj25x48n5C/5PyQX b3D8/ra+afddfrjq6hzDKaNI+mPyZPMQmmGKY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=AK8VJuru84i5wdeMhe5WEpTdJOdUxMHOxZOH3ilxABw=; b=W21B+iFMGgDtup5vGewkPCeEPugcsrQbH9KK4P/ZK7oBZG/lqyQdM+UGq9Pnaa3UGi sWcqIn3/Qw5hMDSn5RloC3pqvT1c9SpE/ubiNUoafJafotAK5oaKtl8AB/h0dOl5mwCw e1a1MT8AGU4VjECHSDzMoUWUM4IuVycICGlZ8pBtIiwdFOpulWwTKFS07c6UBtdMuU+8 QUrLbyqqBX+Qqz//FSYEuqPiusLY9i10rkHhoNSZoNnnannSGOQkgoxSDCH/rC+tIZnx 5LzVaycomZ/R0q3DG8xcf1gOvwjV45/YZGecqTNAPWgPLEJ0oijeMEBpIkp3k7d9awFS dBdg== X-Gm-Message-State: AOPr4FXBH1Ilv1d6W/AjW801HHvPrxpVjglh1c+oIhkg44TjXwkvrq2RgpQKdwLx6YQmUA== X-Received: by 10.98.23.201 with SMTP id 192mr18719058pfx.122.1461225890586; Thu, 21 Apr 2016 01:04:50 -0700 (PDT) Received: from icarus.au.ibm.com ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id uw2sm2650897pac.10.2016.04.21.01.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:04:48 -0700 (PDT) From: Joel Stanley To: linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH v2 04/11] clocksource/moxart: Generalise timer for use on other socs Date: Thu, 21 Apr 2016 17:34:02 +0930 Message-Id: <1461225849-28074-5-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461225849-28074-1-git-send-email-joel@jms.id.au> References: <1461225849-28074-1-git-send-email-joel@jms.id.au> In-Reply-To: <1460627269-21721-1-git-send-email-joel@jms.id.au> References: <1460627269-21721-1-git-send-email-joel@jms.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_010511_452333_4CFE4C1C X-CRM114-Status: GOOD ( 18.33 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:234 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@kernel.crashing.org, jk@ozlabs.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The moxart timer IP is shared with another soc made by Aspeed. Generalise the registers that differ so the same driver can be used for both. As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver so we can express this dependency. Signed-off-by: Joel Stanley --- .../bindings/timer/moxa,moxart-timer.txt | 4 +- drivers/clocksource/Kconfig | 6 ++ drivers/clocksource/Makefile | 2 +- drivers/clocksource/moxart_timer.c | 90 +++++++++++++++++----- 4 files changed, 79 insertions(+), 23 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index da2d510cae47..4569757142f8 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -2,7 +2,9 @@ MOXA ART timer Required properties: -- compatible : Must be "moxa,moxart-timer" +- compatible : Must be one of + - "moxa,moxart-timer" + - "aspeed,ast2400-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number - clocks : Should contain phandle for the clock that drives the counter diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c346be650892..b14ac4db6961 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -411,4 +411,10 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config MOXART_TIMER + def_bool ARCH_MOXART || ARCH_ASPEED + depends on ARM && OF + select CLKSRC_OF + select CLKSRC_MMIO + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dc2b8997f6e6..14fe8172c174 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o -obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o +obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c index 19857af651c1..47ecef0725bd 100644 --- a/drivers/clocksource/moxart_timer.c +++ b/drivers/clocksource/moxart_timer.c @@ -36,45 +36,66 @@ #define TIMER_INTR_MASK 0x38 /* - * TIMER_CR flags: + * Moxart TIMER_CR flags: * * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK * TIMEREG_CR_*_INT overflow interrupt enable bit */ -#define TIMEREG_CR_1_ENABLE BIT(0) -#define TIMEREG_CR_1_CLOCK BIT(1) -#define TIMEREG_CR_1_INT BIT(2) -#define TIMEREG_CR_2_ENABLE BIT(3) -#define TIMEREG_CR_2_CLOCK BIT(4) -#define TIMEREG_CR_2_INT BIT(5) -#define TIMEREG_CR_3_ENABLE BIT(6) -#define TIMEREG_CR_3_CLOCK BIT(7) -#define TIMEREG_CR_3_INT BIT(8) -#define TIMEREG_CR_COUNT_UP BIT(9) - -#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE) -#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE) +#define MOXART_CR_1_ENABLE BIT(0) +#define MOXART_CR_1_CLOCK BIT(1) +#define MOXART_CR_1_INT BIT(2) +#define MOXART_CR_2_ENABLE BIT(3) +#define MOXART_CR_2_CLOCK BIT(4) +#define MOXART_CR_2_INT BIT(5) +#define MOXART_CR_3_ENABLE BIT(6) +#define MOXART_CR_3_CLOCK BIT(7) +#define MOXART_CR_3_INT BIT(8) +#define MOXART_CR_COUNT_UP BIT(9) + +#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) +#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) + +/* + * The ASpeed variant of the IP block has a different layout + * for the control register + */ +#define ASPEED_CR_1_ENABLE BIT(0) +#define ASPEED_CR_1_CLOCK BIT(1) +#define ASPEED_CR_1_INT BIT(2) +#define ASPEED_CR_2_ENABLE BIT(4) +#define ASPEED_CR_2_CLOCK BIT(5) +#define ASPEED_CR_2_INT BIT(6) +#define ASPEED_CR_3_ENABLE BIT(8) +#define ASPEED_CR_3_CLOCK BIT(9) +#define ASPEED_CR_3_INT BIT(10) + +#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) +#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) static void __iomem *base; static unsigned int clock_count_per_tick; +static unsigned int t1_disable_val, t1_enable_val; static int moxart_shutdown(struct clock_event_device *evt) { - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); return 0; } static int moxart_set_oneshot(struct clock_event_device *evt) { - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); writel(~0, base + TIMER1_BASE + REG_LOAD); return 0; } static int moxart_set_periodic(struct clock_event_device *evt) { + writel(t1_disable_val, base + TIMER_CR); writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); - writel(TIMER1_ENABLE, base + TIMER_CR); + writel(0, base + TIMER1_BASE + REG_MATCH1); + writel(t1_enable_val, base + TIMER_CR); + return 0; } @@ -83,12 +104,12 @@ static int moxart_clkevt_next_event(unsigned long cycles, { u32 u; - writel(TIMER1_DISABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; writel(u, base + TIMER1_BASE + REG_MATCH1); - writel(TIMER1_ENABLE, base + TIMER_CR); + writel(t1_enable_val, base + TIMER_CR); return 0; } @@ -119,7 +140,7 @@ static struct irqaction moxart_timer_irq = { .dev_id = &moxart_clockevent, }; -static void __init moxart_timer_init(struct device_node *node) +static void __init __moxart_timer_init(struct device_node *node) { int ret, irq; unsigned long pclk; @@ -150,8 +171,19 @@ static void __init moxart_timer_init(struct device_node *node) clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); + /* Clear match registers */ + writel(0, base + TIMER1_BASE + REG_MATCH1); + writel(0, base + TIMER1_BASE + REG_MATCH2); + writel(0, base + TIMER2_BASE + REG_MATCH1); + writel(0, base + TIMER2_BASE + REG_MATCH2); + + /* Start timer 2 rolling as our main wall clock source, keep timer 1 + * disabled + */ + writel(0, base + TIMER_CR); writel(~0, base + TIMER2_BASE + REG_LOAD); - writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); + writel(t1_disable_val, base + TIMER_CR); + moxart_clockevent.cpumask = cpumask_of(0); moxart_clockevent.irq = irq; @@ -165,4 +197,20 @@ static void __init moxart_timer_init(struct device_node *node) clockevents_config_and_register(&moxart_clockevent, pclk, 0x4, 0xfffffffe); } + +static void __init moxart_timer_init(struct device_node *node) +{ + t1_enable_val = MOXART_TIMER1_ENABLE; + t1_disable_val = MOXART_TIMER1_DISABLE; + __moxart_timer_init(node); +} + +static void __init aspeed_timer_init(struct device_node *node) +{ + t1_enable_val = ASPEED_TIMER1_ENABLE; + t1_disable_val = ASPEED_TIMER1_DISABLE; + __moxart_timer_init(node); +} + CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); +CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", aspeed_timer_init);